Artificial Intelligence (AI) is revolutionizing various sectors, but the complexity and sophistication of emerging network models in AI are increasing, necessitating substantial computational and memory resources for training and deployment. For instance, cutting-edge deep learning models like GPT and BERT contain billions of parameters and require immense computational power for training. Concurrently, edge devices such as smartphones and smartwatches are being equipped with AI capabilities, leading to a surge in demand for tiny machine learning architectures that can function within the constraints of low-power and small form-factor environments. The rise in computational and memory requirements for emerging network models presents significant challenges for hardware design and optimization. Traditional computing architectures, such as CPUs and GPUs, may not be able to meet the demands of these new network models. Therefore, specialized hardware accelerators such as Tensor Processing Units (TPUs), are emerging to cater to the specific needs of AI workloads.

This research topic aims to provide a platform for researchers to publish their latest work on full-stack AI acceleration, including hardware-aware network optimization, compiler and runtime optimization for AI accelerators, emerging computing paradigms for AI, AI accelerator systems and architectures, circuit techniques for AI accelerators, emerging technologies for AI acceleration, and cross-layer co-design for AI acceleration. The aim is to provide a comprehensive view of the state-of-the-art in full-stack AI acceleration and highlight key challenges and opportunities for future research.

To gather further insights into the boundaries of full-stack AI acceleration, we welcome articles addressing, but not limited to, the following themes:
• hardware-aware network optimization,
• compiler and runtime optimization for AI accelerators,
• emerging computing paradigms for AI,
• AI accelerator systems and architectures,
• circuit techniques for AI accelerators,
• cross-layer co-design for AI acceleration,
• reliability and robustness of AI acceleration systems,
• acceleration of emerging AI applications.

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Frontiers in Electronics

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