Materials and Processing for Superconducting Electronics

Superconductor electronics using Josephson junctions (JJs) promise high speed and low power dissipation. JJ-based circuits have been fabricated with nearly 1 million JJs with clock frequencies in the tens of GHz. Power dissipation is minimal compared to equivalent silicon circuitry, which simplifies the heat removal issues and could allow for greater packing density. While cooling to cryogenic temperatures is required, the much smaller power dissipation makes this viable. This technology can potentially be the workhorse for computer server installations and provide significant gains in overall operations per watt. However, integration is an enormous roadblock as typical circuits are implemented with 250 nm feature sizes. This is approximately 50 times larger than currently available silicon technologies and limits the circuit complexity available. Scaling is challenged by multiple problems. Nb layers can have their superconducting properties destroyed by impurity contamination, which requires low-temperature processing. This in turn limits the thermal budget for deposition of insulating layers. These issues preclude the use of damascene processes that are in use in CMOS back-end-of-the-line (BEOL) processing. Sputter deposited Nb has other limitations including difficulty filling small vias and roughness of the polycrystalline surface. The AlO insulator for the JJ barrier is much thinner than the roughness of the Nb film, which contributes to uncontrolled variation in the thickness of the insulator. The insulator forms a tunnel barrier and controls the critical current density, so this variation results in variability in the JJ circuit performance. New material stacks and processing techniques will be necessary to reduce variability and allow junction scaling. Because they are superconducting, resistance is not a concern in the integration of circuits. However, inductance and capacitance now become the dominant parasitics in wiring. Approaches to reduce and control mutual inductance and capacitance become important for higher wiring density. Clock distribution and skew can become dominant design issues. Techniques to reduce parasitics in fabrication are important.

Projections of the power consumption needs for servers to operate the internet indicate that a significant fraction of the world’s power supply could be required for current approaches. Superconducting logic provides a way to offer lower power consumption with higher performance. However, advances in materials and processing are required to get to the desired circuit density. This issue will address efforts to make scalable, high-performance, low-power superconducting electronics. This will include advances in superconducting materials, insulators for both tunnel junctions and wiring isolation, and processing techniques for the manufacture of circuits.

The goal is to provide visibility to new approaches for high-speed, high-density circuits using superconductive electronics. This will highlight new materials and new processing techniques to bring to manufacturing superconducting electronics that are competitive with Si CMOS circuits in density with improved performance and lower power consumption/operation.

We welcome Original Research, Review, and Mini Review and Perspective articles on themes including but not limited to:
· Superconducting metal deposition and uniformity
· Barrier oxide formation and uniformity
· Scalable formation of Josephson Junctions
· Management with new processing of parasitics in superconducting electronics
· Thermal stability and the use of higher temperature compatible materials.