About this Research Topic
High-Performance Computing (HPC) has traditionally focused on a diverse collection of scientific and technical applications covering areas such as engineering design, weather forecasting, drug discovery, stockpile stewardship, computational chemistry, and materials science, among others. The common characteristic is that HPC systems and applications push performance limits across measures of problem size and/or time to solution. It is fair to say that for the history of HPC, performance takes priority, to solve ever larger, complex issues at extremely high throughputs.
Now that supercomputers are approaching or exceeding 50MW of power consumption, future HPC systems will be constrained by energy. The Carbon footprint of AI for LLMs and Generative AI is also a serious concern. Driven by these commercial workloads, Energy Efficient HPC has the capability to be the Post-Moore’s Law challenge problem for computing. Although supercomputers started highlighting energy efficiency using Green500, recent reports have raised the visibility of the challenge, and orders of magnitude improvements in energy-efficient computing performance are needed with tailored benchmarks such as HPCG. Efforts to enhance energy efficiency occur at three levels: individual microchips, computers, and data centers.
The HPC community has a tradition of leveraging commodity computing technology. As such, the HPC community can continue to leverage advances in Cloud Computing/Data Center technology. Are there additional leverage opportunities that will arise from advanced packaging? What could occur if HPC leveraged design methodologies, system integration, and architectural lessons from smartphone microelectronics? Smartphones have a much higher level of energy efficiency of operation, but at the cost of a much higher cost of packaging and integration. As 3D heterogeneous integration is a targeted investment area for the CHIPS Act, the economics could change.
Conversely, government investments in HPC can help it serve as a lighthouse user to drive innovations for first-of-a-kind capabilities that transition back to the broader computing ecosystem. The next era of computing will be enabled by CHIPS Act investments around the world. Near term drivers will be for heterogeneous computing to co-design domain-specialized accelerators that will be integrated with commodity processor cores with advanced packaging, supported by shared memory and a heterogeneous software stack.
The aim of this collection is to engage the scientific community and showcase the latest advances and trends for more efficient HPC systems that can effectively tackle future challenges. Topics of interest include, but are not limited to:
• Energy Efficient architectures and hardware design: Architectures that enable energy efficiency in hardware. Development of energy-efficient processors, memory systems, and other hardware components.
• New concepts in AI to bring energy efficiency to large-scale Scientific Computing Methods and Analysis.
• Energy-aware programming models: Designing runtimes and compiler frameworks that enable developers to write energy-efficient code and utilize power management and monitoring techniques effectively.
• Measurements and Benchmarks: Benchmarks for HPC that brings out energy costs in applications. Measurement techniques needed for estimating runtime energy and power in different aspects of simulations.
Now that supercomputers are approaching or exceeding 50MW of power consumption, future HPC systems will be constrained by energy. The Carbon footprint of AI for LLMs and Generative AI is also a serious concern. Driven by these commercial workloads, Energy Efficient HPC has the capability to be the Post-Moore’s Law challenge problem for computing. Although supercomputers started highlighting energy efficiency using Green500, recent reports have raised the visibility of the challenge, and orders of magnitude improvements in energy-efficient computing performance are needed with tailored benchmarks such as HPCG. Efforts to enhance energy efficiency occur at three levels: individual microchips, computers, and data centers.
The HPC community has a tradition of leveraging commodity computing technology. As such, the HPC community can continue to leverage advances in Cloud Computing/Data Center technology. Are there additional leverage opportunities that will arise from advanced packaging? What could occur if HPC leveraged design methodologies, system integration, and architectural lessons from smartphone microelectronics? Smartphones have a much higher level of energy efficiency of operation, but at the cost of a much higher cost of packaging and integration. As 3D heterogeneous integration is a targeted investment area for the CHIPS Act, the economics could change.
Conversely, government investments in HPC can help it serve as a lighthouse user to drive innovations for first-of-a-kind capabilities that transition back to the broader computing ecosystem. The next era of computing will be enabled by CHIPS Act investments around the world. Near term drivers will be for heterogeneous computing to co-design domain-specialized accelerators that will be integrated with commodity processor cores with advanced packaging, supported by shared memory and a heterogeneous software stack.
The aim of this collection is to engage the scientific community and showcase the latest advances and trends for more efficient HPC systems that can effectively tackle future challenges. Topics of interest include, but are not limited to:
• Energy Efficient architectures and hardware design: Architectures that enable energy efficiency in hardware. Development of energy-efficient processors, memory systems, and other hardware components.
• New concepts in AI to bring energy efficiency to large-scale Scientific Computing Methods and Analysis.
• Energy-aware programming models: Designing runtimes and compiler frameworks that enable developers to write energy-efficient code and utilize power management and monitoring techniques effectively.
• Measurements and Benchmarks: Benchmarks for HPC that brings out energy costs in applications. Measurement techniques needed for estimating runtime energy and power in different aspects of simulations.
Keywords: HPC energy efficient performance, Post-Moore’s Law, challenge problem for computing, CHIPS Act, heterogeneous computing
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