Artificial Intelligence (AI) is rapidly transforming various industries. However, emerging network models in the field of AI are becoming increasingly complex and sophisticated, requiring vast amounts of compute and memory resources for training and deployment. For example, state of-the-art deep learning models such as GPT and BERT contain billions of parameters and require tremendous computational power to train. Meanwhile, edge devices such as smartphones and smartwatches are being equipped with AI capabilities, leading to an explosion in demand for tiny machine learning architectures that can operate within the constraints of low-power and small form-factor environments.
The increase in compute and memory requirements for emerging network models poses significant challenges for hardware design and optimization. Traditional computing architectures, such as CPUs and GPUs, may not be able to meet the demands of these new network models. Therefore, specialized hardware accelerators such as Tensor Processing Units (TPUs), are emerging to cater to the specific needs of AI workloads.
Designing efficient AI systems and accelerators requires a full-stack approach that covers all levels, including algorithms, compiler and runtime, architectures, circuits, and even devices or packaging. This Research Topics aims to provide a platform for researchers to publish their latest work on full-stack AI acceleration.
The goal of this Research Topic is therefore to bring together researchers from academia and industry to present their latest research on full-stack AI acceleration. The topic will cover a wide range of topics related to full-stack AI acceleration, including hardware-aware network optimization, compiler and runtime optimization for AI accelerators, emerging computing paradigms for AI, AI accelerator systems and architectures, circuit techniques for AI accelerators, emerging technologies for AI acceleration, and cross-layer co-design for AI acceleration. We aim to provide a comprehensive view of the state-of-the-art in full-stack AI acceleration and highlight key challenges and opportunities for future research.
Topics of interest include, but are not limited to:
- Hardware-aware network optimization: This topic covers the development of algorithms and techniques that take into account the characteristics of the target hardware platform during neural network design and optimization.
Compiler and runtime optimization for AI accelerators: This topic covers the development of compiler and runtime systems that can optimize AI workloads for specific hardware platforms, including kernel optimization, computation graph optimization, etc.
- Emerging computing paradigms for AI: This topic covers new computing paradigms that can accelerate AI workloads, such as in-memory computing, near-memory computing, approximate computing, stochastic computing, brain-inspired computing, and hyperdimensional computing, etc.
- AI accelerator systems and architectures: This topic covers the design of specialized accelerator systems or architectures for AI/ML workloads.
- Circuit techniques for AI accelerators: This topic covers the development of circuit-level techniques that can improve the performance and energy efficiency of AI accelerators, including low-power design, etc.
- Cross-layer co-design for AI acceleration: This topic covers the co-design of algorithms, architectures, circuits, and devices for AI acceleration, including algorithm-architecture co-design, architecture-circuit-device co-design, and other forms of cross-layer optimization.
- Reliability and robustness of AI acceleration systems: This topic covers the development of techniques and methodologies for ensuring the reliability and robustness of AI acceleration systems under various operating conditions and environments.
- Acceleration of emerging AI applications: This topic covers the acceleration of emerging AI applications, such as robotics, bio-informatics, autonomous systems, and others, that require specialized hardware and software optimizations.
Keywords:
Full stack AI acceleration, Hardware-aware network optimization, AI compiler and runtime optimization, AI accelerator circuit and system, Hardware/network co-design, AI reliability, robustness, privacy, In-memory/near-memory computing
Important Note:
All contributions to this Research Topic must be within the scope of the section and journal to which they are submitted, as defined in their mission statements. Frontiers reserves the right to guide an out-of-scope manuscript to a more suitable section or journal at any stage of peer review.
Artificial Intelligence (AI) is rapidly transforming various industries. However, emerging network models in the field of AI are becoming increasingly complex and sophisticated, requiring vast amounts of compute and memory resources for training and deployment. For example, state of-the-art deep learning models such as GPT and BERT contain billions of parameters and require tremendous computational power to train. Meanwhile, edge devices such as smartphones and smartwatches are being equipped with AI capabilities, leading to an explosion in demand for tiny machine learning architectures that can operate within the constraints of low-power and small form-factor environments.
The increase in compute and memory requirements for emerging network models poses significant challenges for hardware design and optimization. Traditional computing architectures, such as CPUs and GPUs, may not be able to meet the demands of these new network models. Therefore, specialized hardware accelerators such as Tensor Processing Units (TPUs), are emerging to cater to the specific needs of AI workloads.
Designing efficient AI systems and accelerators requires a full-stack approach that covers all levels, including algorithms, compiler and runtime, architectures, circuits, and even devices or packaging. This Research Topics aims to provide a platform for researchers to publish their latest work on full-stack AI acceleration.
The goal of this Research Topic is therefore to bring together researchers from academia and industry to present their latest research on full-stack AI acceleration. The topic will cover a wide range of topics related to full-stack AI acceleration, including hardware-aware network optimization, compiler and runtime optimization for AI accelerators, emerging computing paradigms for AI, AI accelerator systems and architectures, circuit techniques for AI accelerators, emerging technologies for AI acceleration, and cross-layer co-design for AI acceleration. We aim to provide a comprehensive view of the state-of-the-art in full-stack AI acceleration and highlight key challenges and opportunities for future research.
Topics of interest include, but are not limited to:
- Hardware-aware network optimization: This topic covers the development of algorithms and techniques that take into account the characteristics of the target hardware platform during neural network design and optimization.
Compiler and runtime optimization for AI accelerators: This topic covers the development of compiler and runtime systems that can optimize AI workloads for specific hardware platforms, including kernel optimization, computation graph optimization, etc.
- Emerging computing paradigms for AI: This topic covers new computing paradigms that can accelerate AI workloads, such as in-memory computing, near-memory computing, approximate computing, stochastic computing, brain-inspired computing, and hyperdimensional computing, etc.
- AI accelerator systems and architectures: This topic covers the design of specialized accelerator systems or architectures for AI/ML workloads.
- Circuit techniques for AI accelerators: This topic covers the development of circuit-level techniques that can improve the performance and energy efficiency of AI accelerators, including low-power design, etc.
- Cross-layer co-design for AI acceleration: This topic covers the co-design of algorithms, architectures, circuits, and devices for AI acceleration, including algorithm-architecture co-design, architecture-circuit-device co-design, and other forms of cross-layer optimization.
- Reliability and robustness of AI acceleration systems: This topic covers the development of techniques and methodologies for ensuring the reliability and robustness of AI acceleration systems under various operating conditions and environments.
- Acceleration of emerging AI applications: This topic covers the acceleration of emerging AI applications, such as robotics, bio-informatics, autonomous systems, and others, that require specialized hardware and software optimizations.
Keywords:
Full stack AI acceleration, Hardware-aware network optimization, AI compiler and runtime optimization, AI accelerator circuit and system, Hardware/network co-design, AI reliability, robustness, privacy, In-memory/near-memory computing
Important Note:
All contributions to this Research Topic must be within the scope of the section and journal to which they are submitted, as defined in their mission statements. Frontiers reserves the right to guide an out-of-scope manuscript to a more suitable section or journal at any stage of peer review.