Design and implementation of a PV-tied effective inverter with high reliability and low THD for distribution-grid applications

Research has focused on multilevel inverters (MLIs) due to their use in electric vehicles, renewable energy systems, and industrial applications. This paper proposes a new design for a single-phase 21-level asymmetrical MLI for photovoltaic (PV) applications that reduces the number of components, voltage stress, and overall size and cost. Enhanced incremental maximum power point tracking (EINC-MPPT) is used in the PV standalone system to offer a fast dynamic response, track maximum power, and regulate the PV module output voltage. This paper presents a PV-boost DC–DC single-input multi-output (SIMO) converter linked to solar panels to provide supply voltage to the inverter. A level-shifted constant multicarrier sinusoidal pulse width modulation (LSCMSPWM) technique is used to produce a better-synthesized output waveform from the MLI, resulting in low total harmonic distortion (THD) and also meeting IEEE standards. The suggested MLI is simulated in MATLAB/Simulink and tested with a hardware prototype under various load conditions. It is suitable for medium-power and grid-connected renewable energy systems applications. The qualitative and quantitative parameters of the proposed MLI have been evaluated by cost function (CF), number of components, reliability, THD, and total standing voltage (TSV); these parameters are compared with the existing MLIs.

1 Introduction

1.1 Background and motivation

Renewable energy sources are becoming more popular. Environmental consciousness and global energy use are increasing. In contrast, natural resources such as gas, coal, and oil are finite and rapidly depleting (Das et al., 2024). Given the limited availability of these resources, it is now necessary to explore alternative energy sources (Rahimi et al., 2023). Surprisingly, the extensive use of solar energy is leading to growing concerns about the quality, dependability, and coordination of the power grid (Tayyab et al., 2023). To ensure the safe and reliable use of photovoltaic (PV) energy, various countries have established different grid codes (Nyamathulla and Chittathuru, 2023). MLIs are increasingly using PV systems as their primary energy source (Ali Khan et al., 2020). Multilevel inverters (MLIs) have become more common due to their many advantages, such as high power operating capacity, reduced switching losses, outstanding power quality, and low harmonics (Tayyab et al., 2022). These MLIs use several DC sources and power semiconductor switches to produce stepping voltage waveform. Raising their level could improve this voltage waveform (Chappa et al., 2021). It is difficult to achieve MLI reliability and efficiency because of the increased cost and component count of circuits. Three of the most common MLI structures are a neutral point clamped (NPC), a flying capacitor (FC), and a cascaded H-bridge (CHB) (Alhassane Soumana et al., 2022).

1.2 Literature review

According to Omer Prabhu et al. (2020a), CHB MLI provides two different single-phase H-bridge topologies—symmetrical and asymmetrical—that are dependent on DC voltage. In contrast to symmetrical MLIs, asymmetrical ones use DC voltage sources of varying magnitudes. A standard CHB-type inverter will often have a positive, zero, or negative output (Prasad and Dhanamjayulu, 2022). Rao et al. (2018) suggested assessing the output of CHB-type inverters by aggregating the output voltages of each unit. Recently developed control methods suggest CHB inverter topologies, but the full-bridge converter changes DC step outputs into AC. The limited use of full-bridge converters stems from their inability to block higher voltages, while innovative topologies can reduce both single- and three-phase system components (Majeed Shaikh et al., 2023). Some topologies used modular MLIs to provide multilevel outputs with fewer switching devices and DC sources. These topologies use antiparallel bidirectional switches to transfer current in either direction, with minimal switching components (Kumar et al., 2022). Since cascaded subunits reduce switching-device blocking voltage, they resemble modules. The problem with such topologies is that the output level increases the number of switching devices (Sinha et al., 2018). Novel MLI designs are required to provide reduced blocking voltage, more output levels, and fewer components (Bana et al., 2019). This can reduce inverter size and price. Recent work has included a stacked H-bridge MLI architecture with basic units on each side of the complete bridge (Shaik and Dhanamjayulu, 2021).

According to Das et al. (2020), researchers have been studying cascaded MLI topology configurations. There is a singular symmetric MLI that requires fewer switches. An evolutionary algorithm creates a new design and a proven way of controlling both resistive and motor loads, keeping the output voltage stable even when loads change. Babaei et al. (2014) introduced a transistor-clamped H-bridge MLI design by enabling the various output levels for higher voltage and power ratings without necessitating an increase in component ratings. Carrier-based PWM efficiently controls the MLI, which has fewer switching losses at high switching frequencies (Siddique et al., 2020). High-frequency switching applications incur power losses. However, the topologies discussed in Omer et al. (2020b), Das et al. (2018), Sabyasachi et al. (2020), and Sarwer et al. (2020) address the challenges of more components, bulky circuits, high control complexity, THD, and low efficiency. The next step is to categorize standalone inverters as either symmetrical or asymmetrical (Prasad et al., 2021). Using the same value for each DC source indicates a symmetrical arrangement, while using different values for the DC sources results in an asymmetrical design. Meraj et al. (2020) presents two configurations ideal for low- and medium-rated solar power generation. According to Samadaei et al. (2016), FC and NPC MLIs struggle with voltage balance.

MLIs are increasingly used with PV systems as their primary energy source, and a segregated MLI architecture is best for PV integration (Alishah et al., 2017). These systems are highly efficient at electricity generation and have the added benefit of being environmentally friendly (Samadaei et al., 2018). The production of solar PV can be influenced by variations in temperature and solar radiation over time (Narendra Babu, 2024). A PV system’s efficient operation heavily relies on implementing MPPT techniques. Numerous advanced MPPT techniques have been developed to improve the performance of PV systems (Alishah et al., 2016). DC–DC converters effectively handle duty cycle fluctuation to optimize power in MPPT systems. MPPT methods such as hill climbing (HC) and perturbing and observing (P&O) are commonly used due to their straightforwardness (Shaik et al., 2023). Choosing the best MPPT methodology for an application can be challenging because each approach has its advantages and disadvantages. The HC and P&O algorithms are unable to achieve global maximum partial probability (GMPP) in partial shadow (Akbari et al., 2022).

1.3 Challenges

Two-level voltage source inverters are not ideal for greater power applications due to their inability to handle high voltages and the increased electromagnetic interference caused by higher dv/dt (Krishnachaitanya and Chitra, 2021). It is necessary to address these issues to overcome these limitations. MLIs are the best option, offering advantages such as reduced voltage step, improved power quality, less switching losses, minimal harmonics, and improved electromagnetic compatibility (Mustafa et al., 2022). Additionally, as the voltage level rises in diode-clamped MLI systems, capacitor voltage balancing becomes challenging, limiting them to three levels. The utilization of FC-MLIs necessitates an increased number of DC capacitors to accommodate increased voltage levels (Hosseinzadeh et al., 2021). Nevertheless, it is possible to adjust the switching combinations and achieve balanced DC capacitor voltage (Siddique et al., 2019). CHB MLI architecture has gained in popularity and reliability because of its modularity. Nevertheless, every bridge needs a separate DC power supply. Additionally, as the levels grow, there is a greater demand for switches (Thakre et al., 2019). Topologies have been proposed as a cost-effective solution to address power quality concerns and meet high grid-code criteria (Montazer et al., 2021). These topologies are mostly derived from conventional ones; novel optimal MLI designs are required to provide high reliability, low THD, reduced blocking voltage, more output levels, and fewer components. This can reduce inverter size and price.

1.4 Contributions

Some of the most important contributions of this study are:

a. The design of a standalone solar PV system integrated with a PV boost DC–DC SIMO converter and a 21-level MLI architecture that minimizes the number of components and reduces voltage stress, total size, and cost.

b. An EINC-MPPT is used in the PV standalone system to offer a fast dynamic response, track maximum power, and regulate the PV module output voltage.

c. The LSCMSPWM approach delivers a better-synthesized output waveform from the MLI, and the resulting THD of 2.26% also fulfills IEEE standards.

d. The suggested MLI is appropriate for medium-power and grid-connected renewable energy systems applications.

e. The qualitative and quantitative parameters of the proposed 21-level MLI outperform conventional topologies.

1.5 Structure

This study is arranged as follows. The standalone solar PV system and DC–DC boost SIMO converter are presented in Section 1. Section 2 provides a detailed explanation of the suggested 21-level MLI topology operation. In Section 3, both simulation and hardware validation results are presented. Section 4 evaluates and compares the performance parameters of various MLI topologies with the proposed MLI. Finally, Section 5 covers conclusions and future scope.

2 Proposed system

The proposed system’s overall block diagram consists of a solar PV system and a PV boost DC–DC SIMO converter with a proposed MLI (Figure 1). PV technology converts light energy into electrical energy, and solar PV can modify its power production in response to changes in weather conditions and temperature. The suggested method uses a three-level converter with the EINC-MPPT technique to send DC power from PV cells to the proposed MLI architecture. The inverter collects the power that the PV panels generate. A driver circuit will activate switches as needed, employing logic circuits to produce switching pulse patterns via sequence generators. Ultimately, the proposed MLI will provide the load with 21-level output.

Figure 1

Figure 1. Overall proposed novelty block diagram of solar PV integrated MLI.

2.1 Design of the solar PV system

The proposed standalone solar PV system includes a selected solar panel, the 1Soltech 1STH-215-P, which has six series and two parallel units per string. Figures 2A, B display the equivalent circuit of the solar PV cell and the characteristics of the solar PV panel. D_i is the diode, R_Pa, R_Se are the resistances of parallel and series resistances, and n_pa, n_se are the number of parallel and series connected cells, respectively.

From the ideal PV circuit, the diode current can be calculated using Equation 1:

${\mathit{I}}_{\mathit{D}\mathit{i}}={\mathit{I}}_{\mathbf{0}}\left({\mathit{e}}^{\frac{{\mathit{V}}_{\mathit{D}\mathit{i}}}{{\mathit{\gamma }\mathit{V}}_{\mathit{T}}}}-\mathbf{1}\right),(1)$

where $\gamma$ is the ideality constant, saturation current is I₀, thermal voltage V_T = $\left(\frac{{kT}_c}{q}\right)$ depends on the charge of electron q, cell temperature is T_c, and Boltzmann’s constant is k, equal to 1.3,806,503 × 10⁻²³ J/K.

Panel Output power can be calculated by using Equation 2:

${\mathit{P}}_{\mathit{P}\mathit{V}}={\mathit{V}}_{\mathit{P}\mathit{V}}\mathit{x}{\mathit{I}}_{\mathit{P}\mathit{V}}.(2)$

Figure 2

Figure 2. (A) PV cell equivalent circuit. (B) Characteristics of the solar PV panel.

By applying KCL to the PV cell equivalent circuit,

Therefore solar PV output current can be calculated by using Equations 3, 4:

${\mathit{I}}_{\mathit{P}\mathit{V}}={\mathit{I}}_{\mathit{S}}-{\mathit{I}}_{\mathit{D}\mathit{i}}-{\mathit{I}}_{\mathit{p}\mathit{a}}={\mathit{I}}_{\mathit{S}}-{\mathit{I}}_{\mathbf{0}}\left({\mathit{e}}^{\frac{{\mathit{V}}_{\mathit{D}}}{{\mathit{\gamma }\mathit{V}}_{\mathit{T}}}}-\mathbf{1}\right)-{\mathit{I}}_{\mathit{p}},(3)$

${\mathit{I}}_{\mathit{P}\mathit{V}}={\mathit{n}}_{\mathit{p}\mathit{a}}{\mathit{I}}_{\mathit{S}}-{{\mathit{n}}_{\mathit{p}\mathit{a}}\mathit{I}}_{\mathbf{0}}\left({\mathit{e}}^{\left(\frac{\mathbf{1}}{{\mathit{\gamma }\mathit{V}}_{\mathit{T}}}\right)\left(\frac{{\mathit{V}}_{\mathit{P}\mathit{V}}}{{\mathit{n}}_{\mathit{s}\mathit{e}}}+\frac{{\mathit{R}}_{\mathit{s}\mathit{e}}{\mathit{I}}_{\mathit{P}\mathit{V}}}{{\mathit{n}}_{\mathit{p}\mathit{a}}}\right)}-\mathbf{1}\right)-\frac{{\mathit{n}}_{\mathit{p}\mathit{a}}}{{\mathit{R}}_{\mathit{p}\mathit{a}}}\left(\frac{{\mathit{V}}_{\mathit{P}\mathit{V}}}{{\mathit{n}}_{\mathit{s}\mathit{e}}}+\frac{{\mathit{R}}_{\mathit{s}\mathit{e}}{\mathit{I}}_{\mathit{P}\mathit{V}}}{{\mathit{n}}_{\mathit{p}\mathit{a}}}\right),(4)$

The short circuit current (I_S) and irradiance intensity can be calculated using Equations 5, 6:

${\mathit{I}}_{\mathit{s}\left(\mathit{T}\right)}={\mathit{I}}_{\mathit{s}\left(\mathit{T}\mathit{R}\right)}\left[\mathit{\beta }\left(\mathit{T}-{\mathit{T}}_{\mathit{R}}\right)+\mathbf{1}\right],(5)$

where the temperature coefficient is β, reference temperature is T_R, and short circuit current I_S(TR) values are included in the PV data sheets.

Therefore, the irradiance intensity is

${\mathit{I}}_{\mathit{s}\left(\mathit{G}\right)}={\mathit{I}}_{\mathit{s}\left(\mathit{G}\mathit{n}\right)}\frac{\mathit{G}}{{\mathit{G}}_{\mathit{n}}},(6)$

where G_n indicates normal irradiation value.

The saturation current (I₀) can be calculated by Equation 7:

${\mathit{I}}_{\mathit{O}}=\frac{{\mathit{I}}_{\mathit{s}}}{\left({\mathit{e}}^{\frac{{\mathit{V}}_{\mathit{D}\mathit{i}}}{{\mathit{\gamma }\mathit{V}}_{\mathit{T}}}}-\mathbf{1}\right)}.(7)$

2.2 PV boost DC–DC SIMO converter with the EINC-MPPT technique

Figures 3A, B show the connection of a PV boost DC–DC SIMO converter to solar PV panels with EINC-MPPT and solar PV-integrated with PV boost DC–DC SIMO converter for the proposed MLI. This converter consists of switches (S_B, S_L), three DC-link capacitors (C₁, C₂, C₃), and a boost inductor (L) to bring the output voltage of the PV system up to a satisfactory level for the inverter input (Rao et al., 2018). The boost converter employs an EINC-MPPT algorithm to automatically track the MPP of the PV array. The following subsections provide a comprehensive explanation of several aspects of the suggested technique.

Figure 3

Figure 3. (A) EINC-MPPT controlled PV boost DC–DC closed loop SIMO converter. (B) Solar PV integrated with the PV boost DC–DC SIMO converter for proposed MLI.

When switch S_B is on, the output state is isolated, and an inductor (L) and a switch (S) are used to transfer the increasing input current (I_PV). The solar PV output voltage (V_PV) powers the inductor while the switch is on (T_on).

Therefore the inductor voltage can be calculated using Equation 8:

${\mathit{V}}_{\mathit{L}}=\mathit{L}\frac{\mathit{d}\mathit{i}}{\mathit{d}\mathit{t}}.(8)$

When switch S_B is off (T_off), current from the inductor is forced to flow through the load and diode (D). This diode can load the inductor (L) from the voltage source.

Therefore the output voltage of converter is V_Bdc and can be calculated Equation 9:

${\mathit{V}}_{\mathit{B}\mathit{d}\mathit{c}}={\mathit{V}}_{\mathit{P}\mathit{V}}+\mathit{L}\frac{\mathit{d}\mathit{i}}{\mathit{d}\mathit{t}}.(9)$

The boost converter output voltage is controlled by the duty cycle (δ) of the control switch. By altering the switch’s on-time, the output voltage can be precisely controlled.

Therefore, the DC–DC boost converter output voltage can be calculated by Equation 10:

${\mathit{V}}_{\mathit{B}\mathit{d}\mathit{c}}={\mathit{V}}_{\mathit{P}\mathit{V}}\left(\frac{\mathbf{1}}{\mathbf{1}-\mathrm{\delta }}\right),(10)$

where δ = $\frac{{\mathit{T}}_{\mathit{o}\mathit{n}}}{{\mathit{T}}_{\mathit{o}\mathit{n}}+{\mathit{T}}_{\mathit{o}\mathit{f}\mathit{f}}}$.

The inductor and capacitor ratings are calculated using Equations 11, 12:

$\mathit{L}=\frac{{\mathit{V}}_{\mathit{P}\mathit{V}}*\mathrm{\delta }}{\left({\mathit{f}}_{\mathit{s}}*{∆\mathit{I}}_{\mathit{L}}\right)},(11)$

$\mathit{C}=\frac{{\mathit{I}}_{\mathbf{0}}*\mathrm{\delta }}{\left({\mathit{f}}_{\mathit{s}}*{∆\mathit{V}}_{\mathit{B}\mathit{d}\mathit{c}}\right)},(12)$

where ΔI_L is the input current, ΔV_Bdc is the output voltage ripple factors, and f_s is the switching frequency. To obtain a reasonable estimate of the values of the inductor and capacitor, it is recommended limiting ΔI_L to 30% and generally assuming ΔV_Bdc at 5%. The characteristics of the solar PV module DC–DC boost converter requirements are detailed in Table 1.

Table 1

Table 1. Specifications of the solar PV module SIMO converter.

The MPPT controller controls the performance of the boost converter by considering inputs such as temperature, solar radiation, PV array (Voc and Isc) characteristics, and DC link voltage. When the operating point varies around the maximum power point (MPP), especially in situations with rapidly changing irradiance levels, the effectiveness of conventional incremental and conductance MPPT algorithms decreases. To address these problems, an EINC-MPPT technique is implemented; Figure 4 illustrates a flowchart of an EINC-MPPT technique.

Figure 4

Figure 4. EINC-MPPT technique flowchart.

2.3 Proposed 21-level asymmetrical MLI topology

The proposed 21-level MLI architecture consists of fewer components without any inductors, capacitors, and diodes (Figure 5). It consists of only two bidirectional switches (S_A and S_B), eight unidirectional switches (S₁, S₂, S₃, S₄, S₅, S₆, S₇, S₈), and three asymmetrical voltage sources (V₁, V₂, V₃) to achieve 21 voltage levels, with each voltage step V_dc = 40 V and the maximum output voltage 400 V. The DC voltage ratio is crucial for maximizing output voltage and reducing the inverter’s TSV. Based on the recommended MLI architecture, the required component estimations follow.

Figure 5

Figure 5. Proposed 21-level MLI architecture.

2.3.1 Components selection

For the proposed MLI asymmetric operation required DC voltage sources are represented below using Equation 13:

${\mathit{V}}_{\mathbf{1}}=\mathbf{1}{\mathit{V}}_{\mathit{d}\mathit{c}};{\mathit{V}}_{\mathbf{2}}=\mathbf{2}{\mathit{V}}_{\mathit{d}\mathit{c}};{\mathit{V}}_{\mathbf{3}}=\mathbf{7}{\mathit{V}}_{\mathit{d}\mathit{c}}.(13)$

The required DC sources, switches, driver circuits, and maximum output voltage of the proposed MLI are determined using Equations 14–17, where N_Lev indicates the number of levels:

${\mathit{N}}_{\mathit{S}\mathit{o}\mathit{u}\mathit{r}\mathit{c}\mathit{e}\mathit{s}}^{\mathit{P}\mathit{r}\mathit{o}\mathit{p}}=\frac{\left({\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}-\mathbf{3}\right)}{\mathbf{6}},(14)$

${\mathit{N}}_{\mathit{S}\mathit{w}\mathit{i}\mathit{t}\mathit{c}\mathit{h}\mathit{e}\mathit{s}}^{\mathit{P}\mathit{r}\mathit{o}\mathit{p}}=\frac{\left({\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}-\mathbf{1}\right)}{\mathbf{2}},(15)$

${\mathit{N}}_{\mathit{D}\mathit{r}\mathit{i}\mathit{v}\mathit{e}\mathit{r}\mathit{c}\mathit{i}\mathit{r}\mathit{c}\mathit{u}\mathit{i}\mathit{t}\mathit{s}}^{\mathit{P}\mathit{r}\mathit{o}\mathit{p}}=\frac{\left({\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}-\mathbf{1}\right)}{\mathbf{2}}=\mathbf{10}.(16)$

The maximum voltage output (V_o,max) is

${\mathit{V}}_{\mathbf{0},\mathit{max}}^{\mathit{P}\mathit{r}\mathit{o}\mathit{p}}=\frac{\left({\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}-\mathbf{1}\right)}{\mathbf{2}}{\mathit{x}\mathit{V}}_{\mathbf{d}\mathbf{c}}\begin{array}{cc}=& \mathbf{10}\mathbf{\times }\mathbf{40}\mathbf{=}\mathbf{400}\mathbf{V}.\end{array}(17)$

The switches are vital in producing 21 levels using the switching pattern generated by the switching pulse generators. The suggested operational modes of the MLI topology are shown in Figures 6A–U. The various output voltage levels and their corresponding switching states are detailed in Table 2. The current conduction paths are listed in Table 3, and the waveform of the predicted output voltage of the suggested MLI is displayed in Figure 7.

Figure 6

Figure 6. Voltage levels (A–U) of proposed 21-level MLI.

Table 2

Table 2. Proposed MLI switching states.

Table 3

Table 3. Proposed 21-level MLI current conduction paths.

Figure 7

Figure 7. Proposed 21-level MLI expected output voltage waveform.

2.3.2 Level-shifted constant multicarrier sinusoidal pulse width modulation (LSCMSPWM) technique

The proposed MLI needs the right modulation methods to obtain a lower THD that meets the IEEE standard limits and provides good power from the MLI end. Modulation methods enhance the synthesis of the MLI output waveform. To provide gating signals for the power switching devices of the converter, the fundamental frequency is used. In this case, a pulse width modulation technique is used as a control. The optimal reference sinusoidal pulse is associated with level-shifted average level constant multicarrier signals of similar characteristics, which are used to generate gating signals for controlling power converter switches.

This control approach requires (N_Lev−1)/2 average level constant multicarrier signals to achieve the required output voltage levels. The modulation technique generates the model voltage output waveform and logic gate-based (LGB) switching gate pulse generators to store the switching order of every switching device (Figures 8A, B). Ten average-level constant multicarrier pulses (MC_a1 – MC_a10) can produce 21 voltage levels with different shift values but equal frequency. Gate pulse patterns for power converter switching devices are generated by comparing average level constant multicarrier carrier signals with a pure sinusoidal waveform signal (V_ref = |V_m sin (ωt)|).

Figure 8

Figure 8. (A) Expected output voltage waveform of the LSCMSPWM technique. (B) LSCMSPWM technique switching sequence generation for proposed 21-level MLI.

The amplitude of the level-shift constant multicarrier pulse modulated index (M_a) is calculated using Equation 18:

${\mathit{M}}_{\mathit{a}}^{\mathit{i}\mathit{n}\mathit{d}\mathit{e}\mathit{x}}=\frac{\mathit{V}\mathit{m}}{\left[\left({\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}-\mathbf{1}\right)/\mathbf{2}\right]\mathit{x}\mathit{V}\mathit{c}\mathit{r}}.(18)$

The variables Vm and Vcr denote the peak voltage amplitude of the reference signal and the voltage of the constant multicarrier signals, respectively. The proposed 21-level MLI topology requires one fundamental sinusoidal waveform with a 50 Hz frequency as a reference and ten average-level constant multicarrier signals to generate the pulses for power switches. The RMS output voltage of the proposed MLI with its respective modulation index can be calculated using Equation 19:

${\mathit{V}}_{\mathit{a}\mathit{b}}^{\mathit{O}\mathit{u}\mathit{t}}\approx {\mathit{M}\mathit{a}}^{\mathit{i}\mathit{n}\mathit{d}\mathit{e}\mathit{x}}\frac{\mathit{V}\mathit{d}\mathit{c}}{\sqrt{\mathbf{2}}}.(19)$

The optimal output voltage waveform is clipped more frequently as the switching frequency increases. This limits its fluctuation to short intervals.

3 Result analysis

To observe the proposed MLI’s real-time response to various load conditions, it is necessary to simulate and validate the recommended MLI architecture by implementing the prototype. The subsequent sections detail the outcomes of both the simulation and experimental results.

3.1 Simulation results

The simulation results of the solar PV panel and PV-boost SIMO converter output voltages with EINC-MPPT are displayed in Figure 9A. The solar PV panel at MPP generates 112.8 V and is boosted to 400 V using a PV boost converter on the side of a SIMO converter. The PV boost DC–DC SIMO-converter simulated input and output voltages are displayed in Figure 9B. The DC link voltage response comparison for different MPPT techniques is displayed in Figure 9C. The proposed EINC MPPT technique is very effective, with a lower settlement time of 0.085 s than other MPPT techniques.

Figure 9

Figure 9. (A) Simulated output voltage of the solar PV panel and DC–DC boost converter on the side of the SIMO converter. (B) Simulated input and output voltages of the PV boost DC–DC SIMO converter. (C) DC-link voltage response with different MPPT algorithms.

The suggested MLI circuit is modeled and simulated using MATLAB/Simulink software. The switch pulse patterns are produced at a switching frequency of 5 kHz by comparing the multicarrier signals through a 50 Hz sinusoidal signal. The modeled topology is tested for R-load as well as RL-loads. The output voltage and current waveforms of the proposed MLI are shown in Figures 10A–C. These show the output voltage and current waveforms of the MLI with R = 200Ω load and the output voltage and current waveforms of the MLI with an RL-load (R = 200Ω, L = 200 mH), respectively. The simulated FFT analysis THD of 2.06% is displayed in Figure 10D.

Figure 10

Figure 10. (A) Simulated output voltage of proposed 21-level MLI. (B) Simulated output voltage and current waveforms of proposed MLI for R-load. (C) Simulated output voltage and current waveforms of proposed MLI for RL-load. (D) Simulated THD of proposed 21-level MLI.

3.2 Hardware results

The experimental testing of the proposed MLI architecture was conducted, and the component specifications are listed in Table 4. Power-switching IGBT (CM75DU-12H) devices, optocouplers (MCT2E), and asymmetrical DC sources are used to implement this hardware prototype. The dSPACE RT1104 controller is used to generate the switching sequence for each switching device, using optocouplers for activation. The hardware prototype was tested with various load conditions, achieving a 21-level output voltage of 400 V. The voltage and current output waves were examined, and the results were captured using a DSO connected to the prototype via a differential probe. A hardware prototype of the suggested MLI is shown in Figure 11A.

Table 4

Table 4. Specifications of the proposed MLI experimental setup.

Figure 11

Figure 11. (A) Experimental setup of proposed 21-level MLI. (B) Experimental output voltage of the solar PV panel and PV-boost converter. (C) Experimental input and output voltages of the closed loop SIMO converter.

Figure 11B presents the experimental output voltage waveforms of the solar PV panel as well as the PV-boost converter. Figure 11C presents the input and output voltages of the PV-boost DC–DC SIMO converter.

Figures 12A–D present the output voltage as well as the voltage and current waveforms of a proposed MLI for R = 200Ω load and RL-load (R = 200Ω, L = 200 mH), as well as the output voltage waveform for various modulation index (Ma) values, respectively. Figures 13A–D present the output current behavior when the dynamic load changes from R- to RL-load. Figures 14A–E present the output current behavior when the dynamic load changes from RL- to R-. The output voltage THD is 2.26%—in line with IEEE standards.

Figure 12

Figure 12. Proposed MLI experimental waveforms. (A) Output voltage waveform. (B) Output voltage and current waveforms for R-load. (C) Output voltage and current waveforms for RL-load. (D) Output voltage for different modulation index (Ma) values.

Figure 13

Figure 13. Experimental voltage and current waveforms for dynamic load changes from R- to RL-load. (A) 100 Ω to (100 Ω + 200 mH). (B) 200 Ω to (200 Ω + 200 mH). (C) 100 Ω to (100 Ω + 400 mH). (D) 200 Ω to (200 Ω + 400 mH).

Figure 14

Figure 14. Experimental voltage and current waveforms for dynamic load changes from RL- to R-load. (A) {100 Ω + 200 mH} to 100 Ω. (B) {200 Ω + 200 mH} to 200 Ω. (C) {100 Ω + 400 mH} to 100Ω. (D) {200 Ω + 400 mH} to 200Ω. (E) Experimental THD of suggested MLI.

4 Comparative analysis

The proposed 21-level MLI architecture was compared using performance indicators like TSV, THD, losses, efficiency and reliability parameters’ fault rate (FR_T), and mean time to failure (MTTF_T). Procedures and computations for these performance indicators are discussed below. Various qualitative and quantitative parameters are compared, tabulated, and graphically illustrated.

4.1 Total standing voltage (TSV) calculation

TSV is extensively used to choose power switches. All power-switching devices in the design have an influence on TSV (Prasad and Dhanamjayulu, 2022). To calculate the blocked voltage across power-switching devices, V_Sbi = V_i and V_Suni = 2V_i are the voltage stresses on the bi- and uni-directional switches, respectively, where i = 1, 2, n and n is the power switch.

Therefore, the maximum output voltage is calculated using Equation 20:

${\mathbf{V}}_{\mathbf{o},\mathbf{max}}=\mathbf{10}{\mathbf{V}}_{\mathbf{dc}}=\mathbf{400}\mathbf{V}.(20)$

The maximum blocking voltage (MBV) of particular switches can be calculated using Equations 21–23:

${\mathbf{MBV}}_{\mathbf{SA}}={\mathbf{MBV}}_{\mathbf{SB}}=\mathbf{2}{\mathbf{V}}_{\mathbf{dc}},(21)$

${\mathbf{MBV}}_{\mathbf{S}\mathbf{1}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{2}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{3}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{4}}=\mathbf{3}{\mathbf{V}}_{\mathbf{dc}},(22)$

${\mathbf{MBV}}_{\mathbf{S}\mathbf{5}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{6}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{7}}={\mathbf{MBV}}_{\mathbf{S}\mathbf{8}}=\mathbf{7}{\mathbf{V}}_{\mathbf{dc}}.(23)$

The normalized voltage stress (NV_stress) is defined as the ratio of the switch’s V_stress to V_o,max. The V_stress is the true voltage stress. Respective switch voltage stress values are listed in Table 5.

Table 5

Table 5. Voltage stress comparisons across power switches.

Figures 15A, B show each switch voltage stress distribution and the normalized voltage stress (%). The MLI design’s maximum output voltage is 10V_dc, which has 21 levels; however, the algebraic total of DC sources exceeds the switch’s MBV (7V_dc). Despite unequal voltage stress across the switches in the suggested MLI architecture, four switches have a maximum voltage stress of 7V_dc (S₅, S₆, S₇, and S₈). The smallest voltage stress is 20% of the two power switches (S_A and S_B) and 30% intermediate voltage stress of the remaining four switches (S₁, S₂, S₃, and S₄). Therefore, to save money, the suggested MLI design aims to increase DC source intake while minimizing TSV and switches.

Figure 15

Figure 15. (A) Voltage stress distribution. (B) Normalized voltage stress in %.

The TSV is given as the algebraic sum of MBV across individual switches and is expressed in Equations 24, 25, providing the TSV_PU value thus:

$\mathit{T}\mathit{S}\mathit{V}={\mathit{M}\mathit{B}\mathit{V}}_{\mathit{S}\mathit{A}}+{\mathit{M}\mathit{B}\mathit{V}}_{\mathit{S}\mathit{B}}+{\mathit{M}\mathit{B}\mathit{V}}_{\mathit{S}\mathbf{1}}+---+{\mathit{M}\mathit{B}\mathit{V}}_{\mathit{S}\mathbf{8}},(24)$

${\mathbf{TSV}}_{\mathbf{PU}}^{\mathbf{Proposed}}=\frac{\mathbf{TSV}}{{\mathbf{V}}_{\mathbf{O},\mathbf{max}}}.(25)$

The suggested topology TSV^Proposed can be calculated using Equations 26, 27:

${\mathbf{TSV}}^{\mathbf{Proposed}}=\mathbf{2}\left[{\mathbf{MBV}}_{\mathbf{SA}}\right]+\mathbf{4}\left[{\mathbf{MBV}}_{\mathbf{S}\mathbf{1}}+{\mathrm{MBV}}_{\mathbf{S}\mathbf{5}}\right]$

$=\mathbf{4}{\mathbf{V}}_{\mathbf{dc}}+\mathbf{4}\left[\mathbf{3}{\mathbf{V}}_{\mathbf{dc}}+\mathbf{7}{\mathbf{V}}_{\mathbf{dc}}\right]$

$=\left[\mathbf{4}{\mathbf{V}}_{\mathbf{dc}}+\mathbf{12}{\mathbf{V}}_{\mathbf{dc}}+\mathbf{28}{\mathbf{V}}_{\mathbf{dc}}\right]$

${\mathbf{TSV}}^{\mathbf{Proposed}}=\mathbf{44}{\mathbf{V}}_{\mathbf{dc}},(26)$

${\mathbf{TSV}}_{\mathbf{PU}}^{\mathbf{Proposed}}=\frac{\mathbf{44}{\mathbf{V}}_{\mathbf{dc}}}{{\mathbf{10}\mathbf{V}}_{\mathbf{dc}}}=\mathbf{4.4}.(27)$

Therefore, the suggested MLI’s peak inverse voltage (PIV) can be calculated by Equation 28:

${\mathit{P}\mathit{I}\mathit{V}}^{\mathit{P}\mathit{r}\mathit{o}\mathit{p}\mathit{o}\mathit{s}\mathit{e}\mathit{d}}=\left({\mathit{N}}_{\mathit{l}\mathit{e}\mathit{v}}-\mathbf{1}\right)=\mathbf{20}{\mathit{V}}_{\mathit{d}\mathit{c}}.(28)$

4.2 Cost function (CF)

The cost function (CF) can be calculated using some quantitative aspects of the suggested topology, such as a number of DC sources (N_DC), switches (N_Swi), gate driver circuits (N_Dri), diodes (N_Dio), capacitors (N_Cap), and the per unit value of TSV (TSV_pu) of the topology (Prasad et al., 2021). Therefore, the CF can be calculated by Equation 29:

$\mathit{C}\mathit{F}=\left({\mathit{N}}_{\mathit{S}\mathit{w}\mathit{i}}+{\mathit{N}}_{\mathit{D}\mathit{C}}+{\mathit{N}}_{\mathit{D}\mathit{r}\mathit{i}}+{\mathit{N}}_{\mathit{D}\mathit{i}\mathit{o}}+{\mathit{N}}_{\mathit{C}\mathit{a}\mathit{p}}+\mathit{\alpha }{\mathit{T}\mathit{S}\mathit{V}}_{\mathit{P}\mathit{U}}\right).(29)$

In this calculation of the cost function, the weight coefficient α value should be considered lower than 1 as well as larger than 1. In order to best evaluate the cost function, the developed MLI uses an approximation of α values of 0.5 (<1) and 1.5 (>1) (Shaik and Dhanamjayulu, 2021). Equation 30 calculates the cost function per level:

$\raisebox{1ex}{$\mathit{C}\mathit{F}$}\!\left/ \!\raisebox{-1ex}{${\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}$}\right.=\frac{{\mathit{N}}_{\mathit{S}\mathit{w}\mathit{i}}+{\mathit{N}}_{\mathit{D}\mathit{i}\mathit{o}}+{\mathit{N}}_{\mathit{C}\mathit{a}\mathit{p}}+{\mathit{N}}_{\mathit{D}\mathit{r}\mathit{i}}+{\mathit{N}}_{\mathit{D}\mathit{C}}+\mathit{\alpha }{\mathit{T}\mathit{S}\mathit{V}}_{\mathit{P}\mathit{U}}}{{\mathit{N}}_{\mathit{L}\mathit{e}\mathit{v}}}.(30)$

Therefore, CF/N_Lev for the suggested 21-level MLI topology with α values of 0.5 and 1.5 are 1.20 and 1.409, respectively.

4.3 Power loss and efficiency calculation

Two notable power losses occur in multilevel inverters: conduction (P_Cond) and switching losses (P_Swil). Total conduction loss is determined by summing the conduction losses of both IGBTs (P_CSW) and anti-parallel diodes (P_CD) along the current path (Prasad and Dhanamjayulu, 2022). This can be expressed using Equations 31, 32:

${\mathit{P}}_{\mathit{C}\mathit{o}\mathit{n}\mathit{d}}\left(\mathit{t}\right)={\mathit{P}}_{\mathit{C}\mathit{S}\mathit{W}}\left(\mathit{t}\right)+{\mathit{P}}_{\mathit{C}\mathit{D}}\left(\mathit{t}\right),(31)$

${\mathit{P}}_{\mathit{C}\mathit{o}\mathit{n}\mathit{d}}\left(\mathit{t}\right)=\left(\left[{\mathit{V}}_{\mathit{S}\mathit{w}\mathit{i}}+{\mathit{R}}_{\mathit{S}\mathit{W}\mathit{i}}{\mathit{i}}_{\mathit{m}}^{\mathit{\beta }}\left(\mathit{t}\right)\right]+\left[{\mathit{V}}_{\mathit{D}\mathit{i}\mathit{o}}+{\mathit{R}}_{\mathit{D}\mathit{i}\mathit{o}}{\mathit{i}}_{\mathit{m}}\left(\mathit{t}\right)\right]\right){\mathit{i}}_{\mathit{m}}\left(\mathit{t}\right),(32)$

where i_m (4A) is the peak output current. The threshold voltages for power switches and diodes are V_Swi (4 V) and V_Dio (0.7 V). Similarly, R_Swi (0.001Ω) and R_Dio (0.001Ω) represent the power switch on-state resistance and diode, respectively. The datasheet specifies β (0.01) as the power switch specification constant. If N_Swi and N_Dio are the switches and diodes are conducting at the same time (t) to produce each level, then the average conduction loss is expressed using Equation 33:

${\mathit{P}}_{\mathit{C}\mathit{o}\mathit{n}\mathit{d}}=\frac{\mathbf{1}}{\mathbf{2}\mathit{\pi }}\underset{\mathbf{0}}{\overset{\mathbf{2}\mathit{\pi }}{\int }}\left[{\mathit{N}}_{\mathit{S}\mathit{w}\mathit{i}}\left(\mathit{t}\right){\mathit{P}}_{\mathit{C}\mathit{S}\mathit{W}}\left(\mathit{t}\right)+{\mathit{N}}_{\mathit{D}\mathit{i}\mathit{o}}\left(\mathit{t}\right){\mathit{P}}_{\mathit{C}\mathit{D}}\left(\mathit{t}\right)\right]\mathit{d}\mathit{t}.(33)$

Switching loss (P_Swil) is the amount of power used when the switch turns on and off. This loss is calculated for the switch and the antiparallel diode. Equations 34–36 can be used to calculate the turn-on and -off energy loss (E_on, E_off):

$\begin{array}{l}{\mathit{E}}_{\mathit{o}\mathit{f}\mathit{f}-\mathbf{q}}=\underset{\mathbf{0}}{\overset{{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}}{\int }}\left(\mathit{v}\left(\mathit{t}\right)\mathit{i}\left(\mathit{t}\right)\right)\mathit{d}\mathit{t}\\ =\underset{\mathbf{0}}{\overset{{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}}{\int }}\left[\left(\frac{{\mathit{V}}_{\mathit{S}\mathit{W}\mathit{q}}}{{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}}\mathit{t}\right)\left(-\frac{\mathit{I}}{{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}}(\mathit{t}-{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}\right)\right]\mathit{d}\mathit{t},\end{array}(34)$

${\mathit{E}}_{\mathit{o}\mathit{f}\mathit{f}-\mathit{q}}=\frac{\mathbf{1}}{\mathbf{6}}{\mathit{V}}_{\mathit{S}\mathit{W}\mathit{q}}\mathit{I}{\mathit{t}}_{\mathit{o}\mathit{f}\mathit{f}}.(35)$

Similarly,

${\mathit{E}}_{\mathit{o}\mathit{n}-\mathit{q}}=\underset{\mathbf{0}}{\overset{{\mathit{t}}_{\mathit{o}\mathit{n}}}{\int }}\left(\mathit{v}\left(\mathit{t}\right)\mathit{i}\left(\mathit{t}\right)\right)\mathit{d}\mathit{t}=\underset{\mathbf{0}}{\overset{{\mathit{t}}_{\mathit{o}\mathit{n}}}{\int }}\left[\left(\frac{{\mathit{V}}_{\mathit{S}\mathit{W}\mathit{q}}}{{\mathit{t}}_{\mathit{o}\mathit{n}}}\mathit{t}\right)\left(-\frac{{\mathit{I}}^{\prime }}{{\mathit{t}}_{\mathit{o}\mathit{n}}}(\mathit{t}-{\mathit{t}}_{\mathit{o}\mathit{n}}\right)\right]\mathit{d}\mathit{t}$

${\mathit{E}}_{\mathit{o}\mathit{n}-\mathit{q}}=\frac{\mathbf{1}}{\mathbf{6}}{\mathit{V}}_{\mathit{S}\mathit{W}\mathit{q}}{\mathit{I}}^{\prime }{\mathit{t}}_{\mathit{o}\mathit{n}}.(36)$

The time it takes to turn the switch off is t_off, the time to turn it on is a t_on, and the corresponding losses from the switch are E_off-q and E_on-q, respectively. Although V_{SW q} represents the voltage of the switch when it is in the off state, I and I^I represent the currents before and after the switch is turned on, respectively. The total switching losses can be calculated by Equation 37:

${\mathit{P}}_{\mathit{S}\mathit{w}\mathit{i}\mathit{l}}=\mathit{f}\left[{\displaystyle \sum _{\mathit{q}=\mathbf{1}}^{{\mathit{N}}_{\mathit{S}\mathit{W}}}}\left({\displaystyle \sum _{\mathit{i}=\mathbf{1}}^{{\mathit{N}}_{\mathit{o}\mathit{n}-\mathit{q}}}}{\mathit{E}}_{\mathit{o}\mathit{n}\mathit{q}\mathit{i}}+{\displaystyle \sum _{\mathit{i}=\mathbf{1}}^{{\mathit{N}}_{\mathit{o}\mathit{f}\mathit{f}-\mathit{q}}}}{\mathit{E}}_{\mathit{o}\mathit{f}\mathit{f}\mathit{q}\mathit{i}}\right)\right].(37)$

The fundamental frequency is denoted by f, N_on-q, and N_off,-q, and the number of times that the q^th switch is turned on or off during a single fundamental cycle. Therefore, the overall power losses is expressed using Equation 38:

${\mathit{P}}_{\mathit{T}\mathit{o}\mathit{t}\mathit{a}\mathit{l}}={\mathit{P}}_{\mathit{C}\mathit{o}\mathit{n}\mathit{d}}+{\mathit{P}}_{\mathit{S}\mathit{w}\mathit{i}\mathit{l}}.(38)$

The output power can thus be calculated by Equation 39:

${\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}\mathit{p}}={\mathit{V}}_{\mathit{r}\mathit{m}\mathit{s}}*{\mathit{I}}_{\mathit{r}\mathit{m}\mathit{s}}.(39)$

The total efficiency (η) can be calculated using Equation 40:

$\%\mathbf{\eta }=\frac{{\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}\mathit{p}}}{{\mathit{P}}_{\mathit{i}\mathit{n}\mathit{p}}}=\frac{{\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}\mathit{p}}}{{\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}\mathit{p}}+{\mathit{P}}_{\mathit{T}\mathit{o}\mathit{t}\mathit{a}\mathit{l}}}\mathit{x}\mathbf{100},(40)$

where P_outp and P_inp are the output and input powers. Table 6 summarizes the power losses and efficiency of the suggested MLI. The efficiency for various loads is graphically illustrated in Figure 16.

Table 6

Table 6. Summary of the proposed MLI power losses and efficiency.

Figure 16

Figure 16. Efficiency of proposed MLI at different loads.

4.4 Reliability assessment

The reliability study determines the equipment’s predicted lifetime and failure rate, which are crucial to determining the health of any electronic device. Manufacturing organizations can profit from this reliability study as they seek long-lasting, high-performing, and low-maintenance products, and the industry can also estimate the mean time-to-repair and mean downtime to resume operations (Figure 17A). Therefore, an estimation of how long a device will survive is essential. To determine a device’s reliability, several factors are considered.

Figure 17

Figure 17. (A) Mean downtime and mean time to repair a generic component. (B) Flowchart of reliability analysis. (C) Applications of the proposed MLI.

MTTF_T and FR_T are the key reliability assessment requirements. The hazard rate (λ_T) is a prediction of failure over a certain timeframe. When FR is time-invariant, R(t) is reliability. Approximation and precise methods are preferred in power electronic circuit reliability testing. The mean time to the first failure is initially calculated to determine device durability. A high mean-time-to-failure (MTTF_T) indicates reliability. This and the failure rate (FR_T) of a device can be determined using MIL-HDBK 217E standard handbooks (Shaik et al., 2023). The approximation approach simplifies and accurately predicts FR_T values for switches, diodes, and capacitors (mentioned in detail in Table 7), and the flowchart is shown in Figure 17B to calculate the MTTF_T value.

Table 7

Table 7. Failure rates of each component using the approximation method (Shaik et al., 2023).

Furthermore, as shown in Figure 17C, the suggested MLI keeps its self-voltage balanced, a unique quality that makes it suitable for a wide range of applications such as solar PV systems, fuel cells, battery-powered applications, and industrial generators. In addition, the suggested MLI might be used in medium-power micro-grids and grid configurations, offering a reliable solution for the problem of remote electrification.

The total MTTFT is estimated from power electronic circuit element FR values. Equation 41 is used to calculate λ_T:

${\mathit{\lambda }}_{\mathit{T}}=\left[\left({\mathit{\lambda }}_{\mathit{PS}}\times {\mathit{N}}_{\mathit{Swi}}\right)+\left({\mathit{\lambda }}_{\mathit{PD}}\times {\mathit{N}}_{\mathit{Dio}}\right)+\left({\mathit{\lambda }}_{\mathit{PC}}\times {\mathit{N}}_{\mathit{Cap}}\right)\right].(41)$

Equation 42 is used to calculate the power electronic circuit MTTF_T:

$\mathbf{MTT}{\mathbf{F}}_{\mathbf{T}}=\frac{\mathbf{1}}{\mathbf{\lambda }\mathbf{T}}.(42)$

The suggested MLI architecture was compared with numerous quantitative features of the existing MLI topologies, including the number of DC sources (N_DC), power switches (N_Swi), gate drivers (N_Dri), diodes (N_Dio), capacitors (N_Cap), and component count per number of levels (CC/N_Lev). When it comes to qualitative comparisons such as the TSVpu, THD, CF, FR_T, and MTTF_T features, Table 8 presents quantitative and qualitative comparisons of the proposed 21-level MLI with existing topologies. All these comparisons indicate that the suggested 21-level MLI architecture is more economical, cost-effective, and achieves better performance outcomes.

Table 8

Table 8. Quantitative and qualitative comparisons of the proposed 21-level MLI.

5 Conclusion and future scope

This research proposed a novel 21-level MLI architecture for solar PV energy systems with fewer components. In addition, an EINC-based MPPT technique was used for constant PV panel power generation, even in partially shaded situations. The proposed MLI was tested for different loads, including R, RL, R-RL, and RL-R loads. The suggested MLI is simulated in MATLAB/Simulink and validated experimentally using hardware. The qualitative and quantitative comparative analysis with existing architectures demonstrates that the price, size, and TSV of the proposed MLI are reduced. The efficiency is 97.69%, and the CF/N_Lev for different weight coefficient (α = 0.5 and α = 1.5) values is 1.20 and 1.40, respectively. The reliability study parameter of λ_T is 0.0000025 failures/hour and MTTF_T of 400000 h/failure are improved from the findings. The simulated THD is 2.06%, and the experimental THD is 2.26% under the IEEE standards. This suggested architecture can provide high-quality power from PV systems and improve power quality, voltage, and reactive power support for grid-connected systems, FACTS, RES, and EV applications. This research can also be appropriate for a battery storage system that the hotel and residential sectors can supply for emergency and standalone services.

Data availability statement

The raw data supporting the conclusions of this article will be made available by the authors, without undue reservation.

Author contributions

SN: conceptualization, formal analysis, investigation, methodology, software, validation, visualization, writing–original draft, and writing–review and editing. CD: investigation, methodology, project administration, resources, supervision, validation, visualization, and writing–review and editing.

Funding

The authors declare that no financial support was received for the research, authorship, and/or publication of this article.

Conflict of interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors, and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

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Nomenclature

α weight coefficient value

E_on, E_off energy consumption of on–off switches

STM standard testing measurement

R_se, R_pa series and shunt resistances of the PV cell equivalent circuit

K Boltzmann constant

T temperature

δ duty cycle of boost converter

f_S switching frequency

THD total harmonic distortion

CF/N_Lev cost function per level

TSV_pu total standing voltage per unit

V_OC open-circuit voltage of the PV module

I_SC short-circuit current of the PV module

I_Di saturation current of a diode

MPPT maximum power point tracking

EINC enhanced incremental conductance

P&O perturb and observe

V_Suni voltage stress on unidirectional switch

V_ref reference voltage

λ_T total failure rate

λ_PS/λ_PD/λ_PC failure rate of switches/failure rate of diodes/failure rate of capacitors

MTTF_T total mean time to failure

V_rms/I_rms output RMS voltage and current

V_Sbi voltage stress on bidirectional switch

P_Total total power loss

G irradiance

V_cr carrier signal voltage

T_R reference temperature

N_Swi/N_Dri number switches/number of gate driver circuits

V_Swi voltage across the i^th switch

FR_T failure rate

N_Cap/N_Dio number capacitors/number of diodes

R_Swi/R_Dio resistance of the switch/resistance of diode

V_m maximum voltage of the reference signal

M_a modulation index

V_dc DC source voltage

N_Lev/N_DC number of levels/number of DC sources

β power switch specification constant

P_swil switching power losses

P_cond conduction power losses

P_outp output power

P_inp input power

i_m maximum output current

P_CSW/P_CD conduction power loss of switches/conduction power loss of diodes

t total time period

t_off/t_on turn-off and turn-on timings