Design, Validation, and Economic Behavior of a Three-Phase Interleaved Step-Up DC–DC Converter for Electric Vehicle Application

Due to the increasing number of direct current (DC) loads in electric vehicles (EVs), DC–DC converters are widely used in EV applications. Hence, a DC distribution system with DC–DC converters is more efficient. A three-phase interleaved step-up DC–DC converter (ISC) has been proposed for use in electric vehicles. Other uses of the proposed ISC converter include aircraft, satellites, industrial, and traction drives. The proposed converter is subjected to a thorough frequency response study, which is explained in detail. The design technique recommends the proper quantity of switches to be used in the system. The reduction in the number of switches results in a 94% increase in the efficiency of this converter. The economic aspects of ISC, such as cost analysis and its procedure, have been discussed. Design models were checked using MATLAB/Simulink, which was interfaced with the real-time simulator OPAL-RT (OP5700) to ensure that they were appropriate. The results have been presented in detail.

1 Introduction

Recently, the scarcity of fossil fuel resources and rising global warming concerns have become global worries. As a result, electric vehicles (EVs) are the most reliable and realistic solution for adhering to rigorous environmental safety laws (Saadi et al., 2020). The majority of these vehicles are equipped with battery packs capable of powering EVs (Karthikeyan et al., 2019). Power control units like DC–DC converters are considered a vital feature of modern EV chargers and provide a DC link between the battery and the inverter circuit (Babaei et al., 2017; Athikkal et al., 2018). A three-phase interleaved step-up DC–DC converter [ISC] designed for electric vehicles (EV) has been proposed. Additionally, the proposed ISC converter could be used in airplanes, satellites, industrial applications, and traction motor systems. The proposed ISC converter integrates the concepts of boost converter [BC] and interleaved converter [IC] to increase the voltage gain (Bonab et al., 2018; Saravanan et al., 2020). The inputs and outputs are connected in parallel, which ensures a uniform distribution of power in the switching period. This is called interleaving (Guilbert et al., 2016; Zhuo et al., 2019a). The primary characteristics of the boost DC–DC converter topology are as follows: 1) ease of meeting EMI requirements, 2) affordability, and 3) ease of control. The drawbacks of the boost DC–DC converter topology are as follows: 1) large capacitors are required, 2) gain in voltage <4:1, 3) parallel devices are necessary at high power levels, and 4) the rate of ripples is high. The primary characteristics of an interleaved DC–DC converter are as follows: 1) reduced size of passive components and input current ripples, 2) greater voltage gain, and 3) easier to manage. The drawbacks of the interleaved DC–DC converter topology include a larger component count and a significant switching loss. The proposed ISC is intended to overlook the limitations of existing converters. This work proposed an ISC converter to reduce the voltage stress and losses. This efficient method increases efficiency and voltage gain (Kolli et al., 2015; Babaei et al., 2018; Gupta et al., 2020). The proposed ISC converter is a three-phase interleaved step-up DC–DC converter [ISC]. This converter can be operated in a step-up mode of operation (Hegazy et al., 2012; Bharathidasan et al., 2022). Electric vehicle propulsion systems need high input voltage. Electric vehicles are designed and manufactured with high-energy battery packs to store the energy required to produce the required torque and speed (Guilbert et al., 2015; Zhuo et al., 2019b). The semiconductor switch with high resistance in the converter drops the input voltage (Hegazy et al., 2012; Yao et al., 2018). Therefore, semiconductor switches should be used with low equivalent resistance in electric vehicle propulsion applications (Wang et al., 2014a). MOSFETs and diodes have low equivalent resistance, making them ideal for use in converter circuits (Wang et al., 2014b; Padala and Yeddula, 2022). Furthermore, the conduction losses in the windings account for a greater proportion of the voltage drop than in other semiconductor devices in the converter (Kabalo et al., 2012; Wen and Su, 2015). The existing interleaved boost converter topology is similar to interconnecting multiple boost converter topology, which has been used in electric vehicles (Hasan et al., 2017; Zhang et al., 2020). The existing DC–DC converter topology for EVs may be a boost converter, buck-boost, and interleaved converter. These are widely used due to the downsizing features of battery packs. Once the battery packs are downsized, they will reduce the rated voltage (Lee et al., 2000; Khan et al., 2020). Aside from that, the battery pack provides rated voltage, which is enhanced by the DC‐DC converter and is used to connect the battery to the transmission unit (Kirubakaran et al., 2009; Kabalo et al., 2013; Reddy and Sudhakar, 2018), as illustrated in Figure 1.

FIGURE 1

FIGURE 1. Structure of electric vehicle.

The single-phase interleaved converter in electric vehicles is incapable of supplying sufficient voltage to the transmission system (electric motor) (Chakraborty et al., 2019; Khan et al., 2021a). The proposed topology incorporates a three-phase interleaved boost converter that supplies the electric motor unit with sufficient voltage (Zaid et al., 2020; Khan et al., 2021b). The voltage gain, voltage stress, and duty cycle of the ISC converter and the conventional interleaved boost converter are compared (Khan et al., 2021c; Zaid et al., 2021). A PI controller is constructed to achieve the closed response characteristics for the proposed converter (Maalandish et al., 2017; Khan et al., 2021d). The proposed converter’s construction components are compared with the existing DC–DC converters (Li et al., 2012; Khalilzadeh and Abbaszadeh, 2015; Meier et al., 2018). Economic behavior is discussed in terms of a cost analysis of the proposed ISC converter (Aghdam and Abapour, 2016; Krishnachaitanya and Chitra, 2021). Hence, a high step-up is possible with the proposed ISC converter topology shown in Figure 2.

FIGURE 2

FIGURE 2. Proposed three-phase interleaved step-up DC–DC converter [ISC].

The converter topology is designed to combine a three-winding transformer between two phases, and the overall design makes a five-winding transformer. The high step-up operation produces a high output voltage to supply the motor propulsion and overcome the back emf produced in the drive. The windings L₁, L₂, and L₃ are directly connected to the battery. The central windings L_C1 and L_C2 are connected to the cathodes of the diodes D₁, D₂, D_3, and the anodes of the diodes D₄, D₅, and D₅. Additionally, the ISC converter design consists of three power semiconductor switches (S₁, S₂, and S₃) and an output capacitor (C) connected across the load. Additionally, a freewheeling diode is connected across the switches to freewheeling the leakage current through the switch. In this work, the three-phase interleaved boost converter is designed and validated. The steady-state analysis and state space model of this converter topology is derived. Frequency response analysis is also derived from the state space model of this converter, which proves the converter’s stability. In addition to that, the number of switches is reduced by this topology. Hence, switching losses are also being reduced in the ISC converter topology. The proposed ISC converter topology is capable of producing 139 V of output voltage and producing a power range of 881 W. Hence, this converter design attains high voltage gain and is suitable for medium and high-power applications. This proposed ISC converter design is simulated by the MATLAB/Simulink model and interfaced with the real-time simulator OPAL-RT (OP5700). The simulated outcomes clearly show that the proposed DC–DC converter is more competent and highly reliable when compared to other DC–DC converter topologies. The operational modes of the proposed ISC converter are presented in section 2. The steady-state analysis, which explains both voltage gain and voltage stress calculations, is described in section 3. In section 4, the proposed ISC converter’s state space representation is explained. For stability analysis, frequency domain calculations are conducted based on state space modeling. The experimental results and discussions are presented in section 5, economic behaviors are interpreted in terms of cost analysis in section 6 and the article is concluded in section 7.

2 Operating Modes of the Proposed ISC Converter

The structure of ISC is shown in Figure 2. The proposed ISC converter modes of operation are discussed in Figure 3. The characteristic waveforms of BCM are depicted in Figure 4A, whereas the characteristic waveforms of CCM and DCM are depicted in Figure 4B. The turn’s ratio is the ratio of the number of turns in the central winding $\left({\mathit{N}}_{\mathit{c}1}\&{\mathit{N}}_{\mathit{c}2}\right)$ to the number of turns in the external winding $\left({\mathit{N}}_{\mathit{e}1}\mathrm{,}{\mathit{N}}_{\mathit{e}2}\&{\mathit{N}}_{\mathit{e}3}\right)$.

$N=\frac{N_c}{ N_e}.(1)$

FIGURE 3

FIGURE 3. Modes of operation.

FIGURE 4

FIGURE 4. Characteristics waveforms (A) BCM (B) CCM (blue line) and DCM (red Line).

Mode 1: as shown in Figure 3A, switch S1 is initially turned on, while switches S₂ and S₃ are turned off. Current from the battery flows through the winding L₁ and switch S₁. The battery current also conducts L₂ and L₃. Current flows through L₂ to D₂, L_C1, D₄, C, and the load. Current flows through L₃ to D₃, L_C2, L_C1, D₄, C, and the load. The voltage equation is given as

$V_{L1}=V_i,(2)$

$V_{L2}=V_i+V_{Lc1}-V_o,$

$V_{L2}=V_i+N\left(V_{L1}-V_{L2}\right)-V_o,$

$V_{L2}\left(1+N\right)=V_i\left(1+N\right)-V_o,$

$V_{L2}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(3)$

$V_{L3}=V_i+V_{Lc1}+V_{Lc2}-V_o,$

$V_{L3}=V_i+N\left(V_{L1}-V_{L2}\right)+\text{N}\left(V_{L2}-V_{L3}\right)-V_o,$

$V_{L3}\left(1+N\right)=V_i\left(1+N\right)-V_o,$

$V_{L3}=\frac{V_i\left(1+N\right)- V_O}{\left(1+N\right)}.(4)$

Mode 2: as Figure 3B depicts, initially the switch S₂ is ON, and S₁ and S₃ are in an OFF condition. Current from the battery flows to the switch S₂ through the winding L₂. The battery current also conducts L₁ and L₃. Current flows through L₁ to D₁, L_C1, D₅, C, and the load. Current flows through L₃ to D₃, L_C2, D₅, C, and the load.

$V_{L1}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(5)$

$V_{L2}=V_i,(6)$

$V_{L3}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)}.(7)$

Mode 3: as shown in Figure 3C, the switch S₃ is initially turned on, while the switches S₁ and S₂ are turned off. Current from the battery flows through the winding L₃ and switch S₃. The battery current also conducts L₁ and L₂. Current flows through L₁ to D₁, L_C1, L_C2, D₆, C, and the load. Current flows through L₂ to D₂, L_C2, D₆, C, and the load.

$V_{L1}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(8)$

$V_{L2}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(9)$

$V_{L3}=V_i.(10)$

Mode 4: as shown in Figure 3D, the switches S₁ and S₂ are initially turned on, while S₃ is turned off. Current from the battery flows through the winding L₁ and switch S₁, and through the winding L₂ and switch S₂. The battery current also conducts L₃, D₃, L_C2, L_C1, D₄, C, and the load. The voltage equation is given as

$V_{L1}=V_i,(11)$

$V_{L2}=V_i,(12)$

$V_{L3}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)}.(13)$

Mode 5: as shown in Figure 3E, the switches S₂ and S₃ are initially turned on, and S₁ is turned off. Current from the battery flows through the winding L₂ and switch S₂, and through the winding L₃ and switch S₃. The battery current also conducts L₁, D₁, L_C1, D₅, C, and the load. The voltage equation is given as

$V_{L1}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(14)$

$V_{L2}=V_i,(15)$

$V_{L3}=V_i.(16)$

Mode 6: as Figure 3F depicts, initially S₁ and S₃ are turned ON, and S₂ is turned OFF. Current from the battery flows through the winding L₁ and switch S₁, and through the winding L₃ and switch S₃. The battery current also conducts L₂, D₂, L_C1, D₄, C, and the load. The voltage equation is given as

$V_{L1}=V_i,(17)$

$V_{L2}=\frac{V_i\left(1+N\right)-V_O}{\left(1+N\right)},(18)$

$V_{L3}=V_i.(19)$

Mode 7: as Figure 3G depicts, all three switches S₁, S₂, and S₃ are turned OFF. The battery current conducts the winding L₁, L₂, and L₃. Battery current conducts through the windings L₁ to D₁, D₄, C, and the load. Through L₂ current conducts D₂, D₅, C, and the load. Through L₃ current conducts D₃, D₆, C, and the load.

$V_{L1}=V_i-V_o,(20)$

$V_{L2}=V_i-V_o,(21)$

$V_{L3}=V_i-V_o.(22)$

3 Steady-State Analysis

3.1 Continuous Conduction Mode (CCM)

Phase difference Ф = $\frac{{360}^0}{n},$ Ф =120° (n = 3) (23).

The flux produced in the inductor winding is given as

${\Phi }_{c1}={\Phi }_1-{\Phi }_2,(24)$

${\Phi }_{c2}={\Phi }_2-{\Phi }_3.(25)$

The relationship between the central winding and external winding voltage is given as

$V_{LC1}=N\left(V_{L1}-V_{L2}\right),(26)$

$V_{LC2}=N\left(V_{L2}-V_{L3}\right).(27)$

Voltage gain (M) is the ratio of output voltage to the input voltage is given as

$4V_{i}DT+4V_i\left(1-D\right)T-\frac{3V_o}{1+N}\left(1-D\right)T- V_o\left(1-D\right)T=0,$

$4V_i=V_o\left(\frac{3\left(1-D\right)}{1+N}+\left(1-D\right)\right),$

$\frac{V_o}{V_i}=\frac{4\left(1+N\right)}{\left(4+N\right)-D\left(4+N\right)}.$

The expression for the voltage gain is given as

$M_{CCM}=\frac{V_o}{V_i}=\frac{4\left(1+N\right)}{\left(1-D\right)\left(4+N\right)}.(28)$

Figure 5 shows the relationship between voltage gain and duty cycle for the proposed ISC converter with different turns ratio. The curve clearly shows that the proposed ISC converter can provide higher output voltage than the conventional interleaved boost converter and conventional boost converter.

FIGURE 5

FIGURE 5. (A) Duty cycle Vs Voltage gain with different turns ratio (B) Relationship between turns ratio and switch voltage stress.

3.2 Switch Voltage Stress Calculation

The known inductor and capacitor voltages can be used to calculate all of the voltage stress on semiconductor components. The voltage stresses of the power switches and diodes are identical and they are calculated as follows:

$\frac{V_o}{V_i}=\frac{4\left(1+N\right)}{\left(1-D\right)\left(4+N\right)},$

$V_o=\frac{4\left(1+N\right)V_i}{\left(1-D\right)\left(4+N\right)}.(29)$

The total voltage across the capacitor is

$V_c=\frac{4\left(1+N\right) V_i}{\left(1-D\right)\left(4+N\right)},$

$V_c=V_o.(30)$

Since the capacitor is connected in parallel to the load, the voltage across the capacitor is equal to the output voltage.

$\mathrm{Voltage stress of the switches }{\text{V}}_{\text{s}}= \frac{\left(1-D\right)V_o}{\left(4+N\right)D}.(31)$

Voltage stress of the diodes ($V_d$) is given as

$V_d=V_o-V_s=\frac{4\left(1+N\right)V_i}{\left(1-D\right)(4+N)}-\frac{\left(1-D\right)V_o}{\left(4+N\right)D},(32)$

$V_d=\frac{4\left(1+N\right)\left(4-N\right)}{ \left(1-D\right)\left(4+N\right)}.(33)$

Figure 5A shows the Duty cycle Vs Voltage gain with different turn ratios and Figure 5B shows the relationship between voltage stress and turns ratio, N. All of the component voltage stress is lower than the output voltage Vo. The voltage stress on the power switches and diodes is less than 0.5 V. As a result, the proposed ISC converter’s semiconductor components are subjected to low voltage stress.

3.3 Input Current Ripples

The difference between the inductor’s maximum $\left(\Delta i_{L,max}\right)$) and minimum $\left(\Delta i_{L,min}\right)$ values of current are the ISC converter’s input current ripple $\left(\Delta i_{Ln}\right)$.

$\text{Δ}{i}_{Ln}=\text{Δ}{i}_{L,max}-\text{Δ}{i}_{L,min},$

$=\frac{V_i D}{L_{n}f}-\frac{V_{o }D{\left(1-D\right)}^2{\left(4+N\right)}^2}{ 4\left(1+N\right)}.$

Under identical inductor current, output voltage, and input voltage conditions, the duty cycle of the ISC converter and the conventional three-phase interleaved boost converter (IBC) may be represented as

$D=D_T-\sqrt{\left(D_T-3\right)\left(D_T-5\right)} .(34)$

The proposed ISC converter’s reduction in input current ripple when compared to IBC can be represented as

$\text{Δ}{i}_T-\text{Δ}{i}_{Ln}=\frac{V_{i }{D}_T}{L f}- \frac{V_i D}{L_{n}f},$

$= \frac{V_i D_T}{L{ }_{1}f}- \frac{V_{i }\left[D_T-\sqrt{\left(D_T-3\right)\left(D_T-5\right)}\right] }{L_{1}f},$

$=\frac{V_{i }\sqrt{\left(D_T-3\right)\left(D_T-5\right)} }{L_{1}f},(35)$

where $\Delta i_T$ is the input ripple of the IBC and $D_T$ is the duty of the IBC.

3.4 Design of the Inductor and Capacitor

The current ripple is used to design inductors, and the voltage ripple is used to design capacitors. Current ripples of the inductors and the value of inductance are given in Eqs 37, 38.

$\text{Input }\text{current }\text{ripples }\text{of }\text{the }\text{inductors }\text{Δ}{i}_{Ln}=\frac{V_{i}D}{L_{n}f},(36)$

$\text{Range }\text{of }\text{inductor }{L}_n=\frac{V_{i}D}{\text{Δ}{i}_{Ln}f}.(37)$

The capacitors are chosen based on the switching frequency and the output voltage ripple allowed across the capacitance-voltage connection, and other parameters are as follows:

$\text{Output }\text{voltage }\text{ripple }\text{across }\text{the }\text{capacitance-}\text{voltage }\text{Δ}V=\frac{V_{O}D}{RCf},(38)$

$\text{Range }\text{of }\text{capacitor }C=\frac{V_{O}D}{\text{Δ}VRf}.(39)$

The value of the inductor and capacitor is calculated by using Eqs 37, 39.

3.5 Discontinuous Conduction Mode (DCM)

The converter is analyzed in both continuous conduction mode and discontinuous conduction mode. In DCM, Current through the inductors can be calculated.

Mode 1: this mode is the same as CCM’s mode 1 when switch S₁ is ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i}{L_1}DT,(40)$

$i_{L2}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_2} DT,(41)$

$i_{L3}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_3}DT.(42)$

Mode 2: this mode is the same as CCM’s mode 2 when switch S₂ is ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_1}DT,(43)$

$i_{L2}=\frac{V_i}{L_2}DT,(44)$

$i_{L3}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_3}DT.(45)$

Mode 3: this mode is the same as CCM’s mode 3 when switch S₃ is ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_1}DT,(46)$

$i_{L2}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_2}DT,(47)$

$i_{L3}=\frac{V_i}{L_3}DT.(48)$

Mode 4: this mode is the same as CCM’s mode 4 when switch S₁ and S₂ are ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i}{L_1}DT,(49)$

$i_{L2}=\frac{V_i}{L_2}DT,(50)$

$i_{L3}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_3}DT.(51)$

Mode 5: this mode is the same as CCM’s mode 5 when switch S₂ and S₃ are ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_1}DT,(52)$

$i_{L2}=\frac{V_i}{L_2}DT,(53)$

$i_{L3}=\frac{V_i}{L_3}DT.(54)$

Mode 6: this mode is the same as CCM’s mode 6 when switch S₁ and S₃ are ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i}{L_1}DT ,(55)$

$i_{L2}=\frac{V_i\left(1+N\right)-V_o}{\left(1+N\right)L_2}DT,(56)$

$i_{L3}=\frac{V_i}{L_3}DT.(57)$

Mode 7: this mode is the same as CCM’s mode 7, when switch S₁, S_2, and S₃ is OFF. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i-V_o}{L_1}DT,(58)$

$i_{L2}=\frac{V_i-V_o}{L_2}DT,(59)$

$i_{L3}=\frac{V_i-V_o}{L_3}DT.(60)$

Mode 8: as Figure 3H depicts, all three switches S₁, S₂, and S₃ are turned ON, inductor current of the central windings L_C1 and L_C2 becomes zero. Battery current flows through the windings L₁ and S₁, through the windings L₂ and S₂, and through the windings L₃ and S₃. Furthermore, the capacitor C is discharged into the load. The voltage equation is given as

$V_{L1}=V_i,(61)$

$V_{L2}=V_{i },(62)$

$V_{L3}=V_i,(63)$

when switch S₁, S_2, and S₃ are ON. The peak currents through the inductors L₁, L₂, and L₃ can be obtained as

$i_{L1}=\frac{V_i}{L_1}DT,(64)$

$i_{L2}=\frac{V_i}{L_2}DT,(65)$

$i_{L3}=\frac{V_i}{L_3}DT.(66)$

When the volt-sec balance principle is applied to the inductors, the following relationship is obtained:

$D_1=\frac{4D}{\frac{V_o}{V_i}-4},(67)$

$\frac{2V_o }{R}=\frac{1}{2}\left(4+N\right)D\left(D+D_1\right)\frac{V_i}{L{f}_s},(68)$

$\frac{V_o}{V_i}=\frac{\left(4+N\right)D\left(D+D_1\right)R}{4L{f}_s}.(69)$

The normalized inductor time constant $\beta =\frac{4L{f}_s}{R\left(4+N\right)}$.

With the use of Eqs 67, 69, the following quadratic function can be calculated:

${\left(\frac{V_o}{V_i}\right)}^2-4\frac{V_o}{V_i}-\frac{4D^2}{\beta }=0.$

Voltage gain in DCM mode is given by

$M_{DCM}=\frac{V_o}{V_i}=1+\sqrt{1+\frac{D^2}{\beta }}.(70)$

3.6 Boundary Condition Mode Operation

This mode of operation allows the voltage gain of the CCM to be equivalent to the voltage gain of the DCM mode.

$\frac{4\left(1+N\right)}{\left(1-D\right)\left(4+N\right)}=1+\sqrt{1+\frac{D^2}{\beta }}.$

Figure 6 depicts the boundary normalized inductor time constant ${\beta }_{BCM}$ for CCM and DCM which is computed as follows:

${\beta }_{BCM}=\frac{D{\left(1-D\right)}^2{\left(4+N\right)}^2}{4\left(1+N\right)}.(71)$

FIGURE 6

FIGURE 6. Boundary normalized inductor time constant Vs duty cycle curve.

3.7 Efficiency Calculation for the Proposed ISC Converter

The efficiency equation is computed by taking all losses into account. Input power is the sum of all the losses and the output power.

3.7.1 Power Loss in the Switches

Power loss in the switch is the sum of conduction loss and switching loss. Current through the switches S₁, S_2, and S₃ are 2.5, 2.1, and 2.9 A, respectively and the resistance of the switches is 0.3Ω. The total power loss in the switch is 9.4 W which can be computed by the following formula:

$P_{con}=I_{s1}^2{R}_{s1 }+I_{s2}^2{R}_{s2}+I_{s3}^2{R}_{s3},$

$P_{sw}={\displaystyle {\sum }_{i=1}^3\frac{1}{2}{I}_{si}{V}_{si}{t}_{off}f}.(72)$

3.7.2 Power Loss in the Capacitor

Current through the capacitor is 6.3 A and the resistance of the capacitor is 0.1Ω. The total power loss in the capacitor is 4 W which can be found by the following formula:

$P_{capacitor}=I_c^2{R}_c.(73)$

3.7.3 Power Loss in the Diodes

Current through the diodes is D₁ to D₆ is 2.5, 2.9, 3.1, 3.5, 2.8, 3.2 A and the resistance of the diodes is 0.4Ω. The total power loss in the diodes is 25.8 W which can be determined by the following formula:

$P_{diodes}={\displaystyle {\sum }_{i=1}^6{I}_{Di}^2{R}_{Di}}.(74)$

3.7.4 Power Loss in the Inductor Winding

Current through the inductor is 3.2, 3.3, 3.1, 3.8, 3.6 A and the resistance of the inductor is 0.4Ω. The total power loss in the inductor is 23.2 W which can be determined by the following formula:

$P_{inductor}={\displaystyle {\sum }_{i=1}^3{I}_{Li}^2{R}_{Li}}+{\displaystyle {\sum }_{i=1}^2{I}_{Lci}^2{R}_{Lci}}.(75)$

3.7.5 Efficiency of the Proposed ISC Converter

The output-to-input power ratio is known as efficiency. The sum of all losses and output power equals the input power. The efficiency of the proposed ISC converter is 94% which is calculated by the following formula:

$\eta =\frac{P_{out}}{P_{in}}=\frac{P_{out}}{P_{out}+P_{switch}+P_{capacitor}+P_{diodes}+P_{inductor}}.(76)$

4 Stability Analysis OF ISC

The state space model provides the dynamic performance of the converter circuit. It is the mathematical approach to the circuit represented in matrix form with a minimum number of equations called state variables. A state space approach is derived for both the ON and OFF states of the converter circuit. State space analysis is used to derive the transfer function of the ISC.

General state space equation of the system $\dot{X}=Ax+Bu$.

Output equation $Y=Cx+Du$.

Here, $A$ = state matrix,

$B$ = input matrix,

$C$ = output matrix,

$D$ = direct transmittance matrix,

$x$ = state vector,

$u$ = unit vector,

$\dot{X}$ = input vector,

$y$ = output vector.

Applying KVL for mode 1 shown in Figure 3A,

$\frac{d{i}_{L1}}{dt}=\frac{V_{in}}{L_1},$

$\frac{d{i}_{L2}}{dt}=\frac{V_{in}}{L_2}-\frac{V_o}{L_2}-\frac{V_o}{L_{c1}},$

$\frac{d{i}_{L3}}{dt}=\frac{V_{in}}{L_3}-\frac{V_o}{L_3}-\frac{V_o}{L_{c1}}-\frac{V_o}{L_{c2}},$

$\frac{d{V}_o}{dt}=\frac{i_{L2}}{C}+\frac{i_{L3}}{C}-\frac{V_o}{\text{RC}}.$

State space derived for mode 1 is $\dot{X}=A_{1}x+B_{1}u$.

$A_1=\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 0& 0& \frac{-1}{L_2}-\frac{1}{L_{c1}}\\ 0& 0& 0& \frac{-1}{L_3}-\frac{1}{L_{c1}}-\frac{1}{L_{c2}}\\ 0& \frac{1}{C}& \frac{1}{C}& \frac{-1}{RC}\end{array}\right]B_1=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(77)$

Similarly, mode 2 is $\dot{X}=A_{2}x+B_{2}u$.

$A_2=\left[\begin{array}{cccc}0& 0& 0& \frac{-1}{L_1}-\frac{1}{L_{c1}}\\ 0& 0& 0& 0\\ 0& 0& 0& \frac{-1}{L_3}-\frac{1}{L_{c2}}\\ \frac{1}{C}& 0& \frac{1}{C}& \frac{-1}{RC}\end{array}\right]B_2=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(78)$

Similarly, mode 3 is $\dot{X}=A_{3}x+B_{3}u$.

$A_3=\left[\begin{array}{cccc}0& 0& 0& \frac{-1}{L_1}-\frac{1}{L_{c1}}-\frac{1}{L_{c2}}\\ 0& 0& 0& \frac{-1}{L_2}-\frac{1}{L_{c2}}\\ 0& 0& 0& 0\\ \frac{1}{C}& \frac{1}{C}& 0& \frac{-1}{RC}\end{array}\right]B_3=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(79)$

Similarly, mode 4 is $\dot{X}=A_{4}x+B_{4}u$.

$A_4=\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& \frac{-1}{L_3}-\frac{1}{L_{c1}}-\frac{1}{L_{c2}}\\ 0& 0& \frac{1}{C}& \frac{-1}{RC}\end{array}\right]B_4=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(80)$

Similarly, mode 5 is $\dot{X}=A_{5}x+B_{5}u$.

$A_5=\left[\begin{array}{cccc}0& 0& 0& \frac{-1}{L_1}-\frac{1}{L_{c1}}\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ \frac{1}{C}& 0& 0& \frac{-1}{RC}\end{array}\right]B_5=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(81)$

Similarly, mode 6 is $\dot{X}=A_{6}x+B_{6}u$.

$A_6=\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 0& 0& \frac{-1}{L_2}-\frac{1}{L_{c1}}\\ 0& 0& 0& 0\\ 0& \frac{1}{C}& 0& \frac{-1}{RC}\end{array}\right]B_6=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(82)$

Similarly, mode 7 is $\dot{X}=A_{7}x+B_{7}u$.

$A_7=\left[\begin{array}{cccc}0& 0& 0& \frac{-1}{L_1}\\ 0& 0& 0& \frac{-1}{L_2}\\ 0& 0& 0& \frac{-1}{L_3}\\ \frac{1}{C}& \frac{1}{C}& \frac{1}{C}& \frac{-1}{RC}\end{array}\right]B_7=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right].(83)$

Similarly, mode 8 is $\dot{X}=A_{8}x+B_{8}u$.

$A_8=\left[\begin{array}{cccc}0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& \frac{-1}{RC}\end{array}\right]B_8=\left[\begin{array}{c}\frac{1}{L_1}\\ \frac{1}{L_2}\\ \frac{1}{L_3}\\ 0\end{array}\right],(84)$

$\left[A\right]=A_1{d}_1+A_2{d}_2+A_3{d}_3+A_4{d}_4+A_5{d}_5+A_6{d}_6+A_7{d}_7+A_8{d}_8,(85)$

$\left[B\right]=B_1{d}_1+B_2{d}_2+B_3{d}_3+B_4{d}_{4 }+B_5{d}_5+B_6{d}_6+B_7{d}_7+B_8{d}_8,(86)$

where duty cycle, $d=d_1=d_2=d_3=d_4=d_5=d_6=d_7=d_8$.

The state space equation is $\dot{X}=Ax+Bu$.

$\dot{X}=\left[\begin{array}{cccc}0& 0& 0& \left(\frac{-4}{L_1}-\frac{3}{L_{c1}}-\frac{1}{L_{c2}}\right)d\\ 0& 0& 0& \left(\frac{-4}{L_2}-\frac{2}{L_{c1}}-\frac{1}{L_{c2}}\right)d\\ 0& 0& 0& \left(\frac{-4}{L_3}-\frac{2}{L_{c1}}-\frac{3}{L_{c2}}\right)d\\ \frac{4d}{C}& \frac{4d}{C}& \frac{4d}{C}& \frac{-8d}{RC}\end{array}\right] \left[\begin{array}{c}{i}_{L1}\\ i_{L2}\\ i_{L3}\\ V_o\end{array}\right] + \left[\begin{array}{c}\frac{8d}{L_1}\\ \frac{8d}{L_2}\\ \frac{8d}{L_3}\\ 0\end{array}\right]u.(87)$

The output equation is $Y=Cx+Du$.

$Y=\left[\begin{array}{cccc}\mathrm{0}& \mathrm{0}& \mathrm{0}& \mathrm{1}\end{array}\right]\left[\begin{array}{c}{i}_{L1}\\ i_{L2}\\ i_{L3}\\ V_o\end{array}\right]+0 u.(88)$

The closed loop transfer function can be derived for the proposed ISC converter topology from state space Eqs 87, 88 by MATLAB coding.

$H\left(S\right)=\frac{\mathrm{0}\mathrm{.212} s+\mathrm{0}\mathrm{.201}}{\mathrm{1}\mathrm{.062}{s}^4+\mathrm{1}\mathrm{.23}{s}^3+\mathrm{0}\mathrm{.271}s+\mathrm{1}\mathrm{.02}}.(89)$

The transfer function and Bode plot are obtained by MATLAB coding from the matrices of the state space analysis. It is possible to observe the uncompensated bode plot and construct a suitable controller. Generally, a PI controller works best with lower-order systems. The uncompensated bode plot reveals that the system is stable, but contains zeros in the right half plane (Khan et al., 2021a). To maintain an appropriate phase margin, a compensator is designed to eliminate steady-state error and high-frequency disturbances. To optimize the performance of the proposed interleaved Step-up DC–DC converter [ISC], the voltage controller circuit depicted in Figure 7A evaluates both the reference and output voltages. Figure 7B shows the magnitude and phase plots of the interleaved step-up DC–DC converter [ISC]. In MATLAB, the dynamic response of an open loop and a closed loop is calculated. Although the bode plot of the uncompensated system is stable, the phase margin of the system is not desirable, which is 45°. For closed loop stability, the phase margin should be set at 79° to ensure the system has a suitable step response. Both the magnitude and phase plots of the interleaved step-up DC–DC converter are positive, indicating that the ISC circuit design will perform a stable operation. The proposed ISC converter has fewer switches, which decreases switching losses and lowers the circuit cost. The component quantity comparison is discussed in Table 1.

FIGURE 7

FIGURE 7. (A) voltage control loop (B) Bode plot for open loop, closed loop, and compensator.

TABLE 1

TABLE 1. Constructional components comparison of the DC–DC converters.

5 Results and Discussion

To validate the performance of the ISC converter, an 881 W real-time simulation model is built in MATLAB/Simulink and interfaced with OPAL-RT (OP5700) with the specifications defined in Table 2. The converter is operated at a duty ratio of 30 and 40% in continuous conduction mode at a switching frequency of 50 kHz with a measured input voltage of 70 V and an output voltage of 139 V. The overall real-time interfacing setup using the OP5700 is shown in Figure 8. The characteristic waveform of the switch S₁, S₂, and S₃ are shown in Figures 9–11. The voltage across the switch S₁ is 52.9V, S₂ is 53.1 V and S₃ is 55.2 V. Voltage across the diode D₁ and the current waveforms of inductors IL1, IL2 and IL3 show that the converter is in the CCM mode of operation is shown in Figure 12. The inductor current achieves its maximum values linearly at 4.6, 3.9, and 4.2 A. Voltage across the diode D₂ and current through the coil I_LC1 is 3.8 A are shown in Figure 13. The converter’s input voltage and the voltage across the diode D₃ Figure 14. The converter’s input current and the voltage across the diode D₄ are shown in Figure 15. Capacitor voltage and the voltage across the Diode D₅ are shown in Figure 16. If the duty cycle increases from 0.3 to 0.4, the output voltage rises from 65 V to 145 V. The voltage across the capacitor is as same as the output voltage. The output voltage waveform with a measured voltage of 139 V of the converter and the voltage across the diode D₆ are shown in Figure 17. The current through the coil I_LC2 is 3.6 A shown in Figure 18. The output current waveform with a measured current of 6.3 A for 40Ω is shown in Figure 19.

TABLE 2

TABLE 2. Ratings of the components involved in the proposed topology.

FIGURE 8

FIGURE 8. Real-time setup using OP5700.

FIGURE 9

FIGURE 9. Characteristics of switch S₁.

FIGURE 10

FIGURE 10. Characteristics of switch S₂.

FIGURE 11

FIGURE 11. Characteristics of switch S₃.

FIGURE 12

FIGURE 12. Current through the coil I_L1.

FIGURE 13

FIGURE 13. Current through the coil I_L2. The voltage across the diode D₁ Voltage across the diode D₂.

FIGURE 14

FIGURE 14. Input Voltage Vin and Diode Voltage D₃.

FIGURE 15

FIGURE 15. Input Current Iin and Diode Voltage D₄.

FIGURE 16

FIGURE 16. Capacitor Voltage Vc and Diode Voltage D₅.

FIGURE 17

FIGURE 17. Output Voltage Vo and Diode Voltage D₆.

FIGURE 18

FIGURE 18. Current through I_LC2 and V_out at D = 0.3 and 0.4.

FIGURE 19

FIGURE 19. Output current of the ISC converter.

In Figure 20A, the efficiency of the converter is plotted against the output power, and when the output power increases, the efficiency gradually increases as well. The proposed converter’s efficiency increases to 94% when the output power is increased from 400 to 881 W.

FIGURE 20

FIGURE 20. (A) ISC converter’s Efficiency with Various Output Power (B) Power Loss in various components.

The loss distribution among semiconductor components is depicted in Figure 20B. According to the same chart, the highest power loss in the diodes (D₁ to D₆) is 41.6%. Switch losses (S₁, S₂, and S₃) are 14.3%. Inductors and capacitors have total losses of 34.5 and 9.6%, respectively.

6 Economic Behavior OF the ISC Converter

Once examining economic behavior, it is necessary to take switching losses and the cost function into account. The number of power switches in the topology impacts the implementation cost. The performance of the equipment is proportional to its tangible cost. Costs are categorized as variable or fixed. The cost structure varies by product. The goal of this study is to determine the converter topology’s cost. The variable cost of the product is related to the quantity manufactured, while the variable cost per unit is fixed. This results in a price discrepancy for the product; this is referred to as the “tangible cost,” and it is used to estimate the price of the equipment.

However, because the fixed cost per unit changes according to the system, selecting products based on their fixed costs may result in economic loss. This is suited for products in modest quantities. The ISC converter’s cost was estimated using a cost estimation tool that adheres to industry standards. The cost function of the ISC converter is proportional to the number of devices and DC voltage sources connected. Typically, the cost of electronics is dictated by the voltage, current, and power rating of the product. Thus, these are the components that contribute to the cost assessment of the product. Figure 21A depicts the elements included in the proposed ISC converter’s cost evaluation. The ISC Converter’s implementation costs have been divided into four categories: primary level, secondary level, tertiary level, and final level. The entire sequence necessary to determine the cost of implementing the ISC is depicted in Figure 21B. ISC converter’s total system cost comprises the initial installation cost, downtime costs, and power loss costs. The installation cost of the ISC converter comprises the investment in a power converter system. Three-phase ISC converters used in EV systems are composed of the following components: a battery, three power switches, six diodes, five inductors, and a capacitor. According to (Aghdam and Abapour, 2016), the cost of a single power MOSFET, a single inductor, a single diode, and a single capacitor is $3.6, $1.15, $1.9, and $1.5, respectively. As a result, the total cost of installation of three-phase ISC converters decreases.

${\text{C}}_{\text{install}}=\left(\mathrm{3}\mathrm{.6}\text{ ∗ }{N}_{Sw}\right)+\left(\mathrm{1}\mathrm{.9}\text{∗}{N}_D\right)+\left(\mathrm{1}\mathrm{.15}\text{∗}{N}_{ind}\right)+\left(\mathrm{1}\mathrm{.5}\text{ ∗ }{N}_c\right)+\text{b}\text{attery }\text{c}\mathrm{ost,}(90)$

Where, $N_{Sw}$ = number of switches, $N_D$ = number of diodes, $N_{ind}$ = number of inductors, and $N_c$ = number of capacitors.

FIGURE 21

FIGURE 21. (A) Factors considered for Cost of the converter (B) Process for estimating the ISC’s implementation costs.

Downtime is defined as any period of time during which equipment is neither working nor producing. One week is necessary to replace the failed equipment. For a downtime period, a financial loss of $2.5 per hour would be assumed. To calculate downtime costs, N years and mean time between failures (MTBF) are taken into account. MTBF is the average time between system failures.

$C_{down}=\frac{N}{MTBF}\ast \left(\mathrm{24}\ast \mathrm{7}\ast \mathrm{2}\mathrm{.5}+{\text{C}}_{\text{install}}\right).(91)$

Additionally, the cost of power loss is estimated to be $0.1 per kilowatt-hour. As a result, the total cost of power loss over 1 year is as follows:

$C_{loss}=P_{loss}\ast \mathrm{365}\ast \mathrm{24}\ast \mathrm{0}\mathrm{.1}\mathrm{.}(92)$

The following calculation can be used to determine the total cost of the ISC:

${\text{C}}_{\text{tot }}={\text{C}}_{\text{install}}+C_{down}+C_{loss}.$

The total cost of the proposed converter for 15 years is $1,211.3 and for 30 years $2387.1. Cost comparison of conventional interleaved converter Vs ISC is shown in Table 3. The calculated total cost of the proposed ISC is much lower than the conventional interleaved converter. Hence, it is economical.

TABLE 3

TABLE 3. Cost comparison of conventional interleaved converter vs. ISC.

The cost comparison clearly shows that the installation cost and the downside cost are nearly the same for both converters and that the cost of loss is higher in a conventional interleaved converter. In ISC, the cost of loss is very low than in conventional interleaved converters. Hence, the proposed ISC reduces the cost of loss. As a result, the total cost is reduced for ISC. The proposed converter excels over conventional converters in terms of switching losses, efficiency, stability, and cost function. As a result, the proposed topology can be used in commercial applications because it is economically efficient.

7 Conclusions

The three-phase interleaved step-up DC–DC converter [ISC] has been proposed, and the topology performance has been validated by the analysis of stability in the frequency domain. The proposed converter operates in both closed and open loop modes, which results in the proposed converter ensuring stable operation. The operating concepts and theoretical analysis of CCM and DCM are thoroughly explored. The proposed topology has been compared to the existing topology in terms of its constructional features, which clearly shows the proposed converter has the minimum number of switches. Due to the reduction of switches in the proposed ISC converter, which reduces switching losses and lowers the cost of making the converter circuit. Hence, it is economically efficient. The implementation of the proposed topology has been performed in the environment of MATLAB/Simulink and interfaced with OPAL-RT (OP5700). It has also been demonstrated through experimental results that voltage stress on the semiconductor components is smaller than that of the output voltage. The real-time implementation of a maximum power rating of 881 W was tested, and the maximum efficiency was observed to be 94%. Additionally, it was revealed that decreasing the input voltage reduces efficiency due to increased conduction losses. The converter performed effectively under steady-state and dynamic-state behavior, and the experimental results were consistent with the theoretical predictions. The economic behavior of ISC has been discussed and compared with the conventional interleaved converter. The overall analysis clearly shows the proposed ISC is superior in terms of voltage gain, switching losses, efficiency, stability, and cost function. Since this topology is promising for EV applications.

8 Future Scope

At a future point, a bidirectional version of the proposed ISC converter topology could be developed, with both step-up and step-down operations performed in the same circuit. At present, the converter is in step-up mode. The switches are connected in parallel with the diode. Once the main switch is turned off, the device enters step-down mode, and energy is saved in the battery, thereby achieving bidirectional operation. Bidirectional mode refers to the flow of power from the source to the load and vice versa. Furthermore, soft switching techniques are used. To minimize switching losses, soft switching approaches employ resonant mechanisms to turn on at zero voltage and turn off at zero current. The reliability, stability, switching losses, economic efficiency, and economic behavior of the bidirectional version of the proposed ISC converter topology will be incorporated.

Data Availability Statement

The original contributions presented in the study are included in the article/Supplementary Materials; further inquiries can be directed to the corresponding author.

Author Contributions

All authors listed have made a substantial, direct, and intellectual contribution to the work and approved it for publication.

Conflict of Interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s Note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors, and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

Supplementary Material

The Supplementary Material for this article can be found online at: https://www.frontiersin.org/articles/10.3389/fenrg.2022.813081/full#supplementary-material

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