A low-cost current flow controlling interline hybrid circuit breaker combined with SCR and H-bridge sub-module

A massive number of DC circuit breaker is usually necessary to be installed to protect HVDC grids from DC faults, this will lead to high capital costs because large number of expensive IGBT-in-series are used. In this paper, an interline hybrid circuit breaker is proposed by the combination of SCR string and a small number of H-bridge modules (SCR-IHCB). The proposed SCR-IHCB has the capacity of blocking DC fault of two adjacent lines respectively by sharing only one main breaker branch (MB) mainly composed of low-cost SCR string and H-bridge module instead of IGBT-in-series string. The interline current flow control function is also integrated. Hence it has advantages of simple and compact topology, economical design compared with typical IGBT based HCB solutions. The operation process of the proposed SCR-IHCB is discussed in detail, and the performance is verified by MATLAB Simulink simulation and scale-down prototype experiment.

1 Introduction

Nowadays, HVDC grids have attracted significant attention, due to its inherent advantages such as flexible control of active and reactive power, low loss, system redundancy, and power reliability (Flourentzou et al., 2009; Akhmatov et al., 2014). While the HVDC grid offers several advantages, its engineering application still faces several challenges, one of which is the DC fault handling. The DC circuit breakers (DCCBs) is considered as an essential technology to isolate the fault area and maintain normal operations of non-fault areas in HVDC grids. There are three main groups of DCCB: mechanical DCCBs (Shi et al., 2015; Lin et al., 2016), solid-state DCCBs (Corzine and Ashton, 2012; Sano and Takasaki, 2014; Chang et al., 2016; Keshavarzi et al., 2017; Li et al., 2019; Wang et al., 2019; Shu et al., 2020; Zhang et al., 2020; Xu et al., 2021), and hybrid DCCBs(HÄFNER and JACOBSON, 2011; Sander et al., 2018). The hybrid DCCBs combine the merits of mechanical DCCBs and solid-state DCCBs and therefore is considered as an acceptable solution in HVDC grids. The classic hybrid DCCB (HCB) topology contains a main breaker branch (MB), an energy absorption branch and a transfer branch, the transfer branch consists of an ultra-fast mechanical disconnector (UFD) in series with load current switch (LCS). There are two main groups of HCBs based on the different MB technical routes.

One of the technical routes is IGBT based MB, the classic IGBT-in-series based HCB has been proposed by ABB and successfully tested (HÄFNER and JACOBSON, 2011; Sander et al., 2018). The State Grid Corporation of China (SGCC) proposed a full-bridge modular based MB to avoid the problem of IGBT-in-series synchronization control and has been used in Zhangbei four-terminal MMC-HVDC (Jia et al., 2020; Jinkun et al., 2020.). In order to further reduce the system cost, some integration solutions are proposed, multi-line DC circuit breakers are integrated into one equipment to reduce the number of unidirectional MBs (Liu et al., 2017; Majumder et al., 2017; Mokhberdoran et al., 2018a; Kontos et al., 2018; Li and Wang, 2018; Xiao et al., 2020; Guo et al., 2021; Wang et al., 2022), another solution integrated HCBs and current flow controllers (CFCs) into one equipment is proposed in (Cwikowski et al., 2018; Mokhberdoran et al., 2018b; Zhu et al., 2022.) to reduce the system loss. But there are still some drawbacks to the hybrid DCCB topology as follows:

(1) Large number of series connected full-controlled semiconductors, such as IGBTs or IGCTs, in the main breaker increase the investment severely (Chen et al., 2018).

(2) In future, large DC grids fault currents may exceed the interruption capacity of IGBT under serious fault conditions. The parallel connection of IGBTs is needed but also introduces challenges in terms of construction cost (Dong et al., 2021).

Another technical route is SCR based MB, The SCR based MB has advantages of larger capacity, and lower price. Since the current conducted through the SCR need to reach a value below its threshold current during the turn-off process of SCR, apply a reverse voltage is one of the possible solutions to ensure fast transition from conducting to blocking. The most important issue when designing an SCR-based HCB is reliably to generate a reverse voltage on SCR during the turn-off process so as to make the current conducted through the SCR reach a value below its threshold current(Jamshidi Far and Jovcic, 2018).

Coupled inductors or Z-source schemes are used to generate the required reverse voltage on SCR during the turn-off process in (Ray et al., 2019). In those schemes, the transient fault current through capacitors is used to generate a reverse voltage on SCRs, hence those schemes can only be passively turned-off in the condition of the high current rising rate.

A thyristor full-bridge based HCB topology is proposed in (Guo et al., 2020), which can pre-charge the capacitor with DC system voltage, and the reverse voltage is generated by discharge process of pre-charged capacitor. The full-bridge structure is used to pre-charge the capacitor with dc system voltage and switch the fault current path, the use of large number of thyristor strings also increases the system cost.

A SCR-HCB with multiple branches is proposed by Alstom in (Grieshaber et al., 2015), the capacitance voltage difference of different branches is used to generate the required reverse voltage. The inductor is no longer needed, but if n branches are required for each HCB, 2n number of thyristor strings are required for two adjacent lines, which also increases the number of components in the whole DC grid system.

A DCCB topology combing many SCRs with a few IGBTs-in-series is proposed in (Shu et al., 2020). The required reverse voltage can be generated by controlled IGBT. However, each DCCB requires two additional IGBT strings, the utilization of the device needs to be increased in multi-terminal system.

In this paper, an interlink hybrid DC circuit breaker (IHCB) based on the concept of sharing only one SCR string MB between two lines is proposed (SCR-IHCB) to increase the utilization of the device. Only a few H-bridge submodule is embedded in to generate the required reverse voltage of SCR turn-off process, and the current flow controlling function is also integrated into the IHCB. No additional capacitor pre-charge circuits and inductors are required, the proposed solution can interrupt the short circuit current of two lines independently and control the current flow if necessary. Therefore, compared to the traditional DCCB/CFC schemes, the proposed topology is simple and economical.

2 Proposed topology

2.1 Basic structure of proposed SCR-IHCB

A novel IHCB is proposed in this paper and its detailed structure is shown in Figure 1. MB is composed of an anti-parallel SCR string and a H-bridge sub module, connecting line 12 and line 13. MOV₂ is used to protect IGBTs in H-bridge sub module. The transfer branch consisting of LCS and UFD is installed on each line. C₁ can be charged through T₁ to the limiting voltage of MOV₁ to block the fault current and absorb the residual energy of the system.

FIGURE 1

FIGURE 1. Proposed SCR-IHCB topology and installation position in system. (A) Proposed topology; (B) Three-terminal meshed HVDC system under study.

There are three modes of operation: normal operation without current flow controlling (bypass mode), normal operation with current flow controlling (CFC mode), fault current blocking mode. Obviously, higher system integration, lower volume and cost are achieved because only 1 MB mainly based on low-cost SCR string is used, and CFC function are integrated together.

2.2 Operation principles in different mode

2.2.1 Bypass mode

When the multiterminal HVDC (MT-HVDC) system is running normally, LCS₁/LCS₂ and UFD₁/UFD₂ are all conducted, the SCR string (T₀) and H-bridge submodule are bypassed. There is no additional conduction loss and switching loss of semiconductor devices except LCS₁/LCS₂.

2.2.2 Current flow control mode

When the current flow needs to be adjusted, the proposed SCR-IHCB can work in CFC mode, the working principle is similar with other interline power flow controllers as shown in (Balasubramaniam et al., 2015; Sau-Bassols and Gomis-Bellmunt, 2017). The possible states concerning the available switches are summarized in Table 1.

TABLE 1

TABLE 1. Switching states for CFC mode.

Where “1” represents the switch is ON and “0” represents the switch is OFF. In Figure 2, one pair of states (state1 and state 2 in Table 1)f of current flow scenarios (I₁₂ and I₁₃ are going out the SCR-IHCB and I₁ is entering) are considered as an example. In order to transfer power from line13 to line 12, the CFC should switch continuously in state 1 and state 2 by alternating conduction of S₁ and S₃.

FIGURE 2

FIGURE 2. Operation stages of SCR-IHCB. (A) State 1; (B) State 2.

Below, the analytical analysis of the SCR-IHCB is performed for the pair of states (state 1 and state 2) presented before. Then, the analysis can be extended to the whole range of current configurations.

Taking state 1 as an example, capacitor C₂ is charged by I₁₃, which is equivalent to inserting a negative voltage in series with line 13. In state 2, capacitor C₂ is discharged by I₁₂, which is equivalent to inserting a positive voltage in series with line 12. Assuming D is the duty cycle of state 1. The average model of the three-terminal system with SCR-IHCB can be described as Figure 3.

FIGURE 3

FIGURE 3. Average model of three-terminal DC grid with SCR-IHCB in current control mode.

2.2.3 Fault blocking mode

Take the DC short circuit fault of line12 when SCR-IHCB works in bypass mode as an example, the DC fault current blocking principle is given in Figure 4. Before the fault occurs, the load currents may flow through the low-loss transfer branches in bypass mode as shown in Figure 4A or in CFC mode such as shown in Figure 2.

FIGURE 4

FIGURE 4. Operation of the SCR-IHCB for the transmission line fault. (A) Before t₂. (B) t₂-t₃. (C) t₃-t₄ (D) t₄-t₅ (E) t₅-t₆ (F) t₆-t₇.

Stage 1(t_1-t₃): If a fault occurs on line12 at t₁ and is detected at t₂, S₅, S₇ and T₀ will be switch on immediately, and then the IGBTs in LCS₁ will all be switched off at t₃, as shown in Figure 4B. The fault current is then commutated from transfer branch to the main breaker branches, and UFD₁ will open within 2 m.

Stage 2(t_3-t₅): With UFD₁ in open position at t₄ as shown in Figure 4C. Then S₇ switched off, and the S₈ will be switched on, thyristor T₁ will also be turned on immediately as shown in Figure 4D. Initially, T₀ still is on-state, capacitor voltage V_c2 may suddenly increase in a short time, but its maximum value is strictly limited to the protection voltage V_MOV2 by the parallel MOV₂, that will protect the IGBT S₅-S₈ from exceeding its maximum withstand voltage. Fault current will keep charging C₁ from zero-voltage state. The capacitor voltage V_c1 gradually increases from zero but it is smaller than the capacitor voltage of V_c2 which has been pre-charged in interline CFC mode, and a reverse voltage V_T0 (V_T0 = V_c1(t) −V_c2) will hereby be generated, the equivalent circuit is shown in Figure 5. The duration of reverse voltage should be larger than the requested recovery time, and the SCR string will be turn off reliably at t₅ as shown in Figure 4E.

FIGURE 5

FIGURE 5. Implified equivalent circuit of current commutation process. (A) t₃-t₄ (B) t₄-t₅.

Stage 3(t_5-t₇): The fault current continuously charges C₁. When V_c1 reaches the protection voltage of MOV₁ at t₆, the current flowing through C₁ is transferred to MOV₁ as shown in Figure 4F. Until fault current decreases to value that no longer maintain D₁ conduction, the fault is cleared at t₇.

3 Parameters design and analysis

3.1 Analysis of current commutation

Based on the fault blocking mode described in Section 2, the process of current commutation starts when the IGBTs in LCS₁ are switched off at t_3. Prior to the capacitor C₁ is inserted at t₄, the fault current is fed into the fault node through healthy nodes, it means the current of other stations will inject into line12, the equivalent circuit is given in Figure 5A. Ignoring the resistance of the IGBTs and thyristor which are much less than line resistance, the fault current i_fault can be written as below:

$\begin{array}{c}{i}_{fault}\left(t\right)=i_{12}\left(t\right)+i_{13}\left(t\right)=\frac{V_{\mathit{1}}}{R_{12}}\left(1-e^{\frac{-{tR}_{12}}{L_{12}}}\right)+\frac{V_3}{\left(R_{12}+R_{13}\right)}\left[1-e^{\frac{-t\left(R_{12}+R_{13}\right)}{\left(L_{12}+L_{13}\right)}}\right]\left(t_1\le t\le t_4\right)\end{array}(1)$

Where V₁ and V₃ are the voltage of station 1 and station 3 that assumed to remain constant value throughout the process, R₁₂ and L₁₂ is the resistance and inductance value of line12 to fault point, R₁₃ and L₁₃ is the resistance and inductance value of line13.

From t₄ to t₅, the capacitor C₁ and C₂ are inserted into the system, the simplified equivalent circuit can be seen in Figure 5B. For capacitor C₂, its voltage has a sudden increase in a short time and the maximum value is the clamping voltage of MOV_2. The current i₁₂ will charge the capacitor C₁ from zero until trigger the clamping voltage of MOV₁ at t₆. According to Figure 5B, the differential equations from t₄ to t₅ can be expressed as:

$\left\{\begin{array}{l}{L}_{12}\frac{\mathrm{d}{i}_{12}}{\mathrm{d}t}+V_{\mathrm{c}1}=V_1\\ i_{12}={\mathrm{C}}_1\frac{\mathrm{d}{u}_{{\mathrm{c}}_1}}{\mathrm{d}t}\\ V_{\mathrm{c}1}\left(0\right)=0\\ V_{\mathrm{c}2}=V_{\mathrm{c}\mathrm{l}\mathrm{a}\mathrm{m}p2}\\ i_{12}\left(0\right)=i_{12}\left(t_4\right)\end{array}\right.(2)$

where V_clamp2 is the clamping voltage of MOV₂, the voltage of the capacitor C₁ from t₄ can be obtained:

$V_{\mathrm{c}1}\left(t\right)=V_1-V_1\cos \frac{1}{\sqrt{L_{12}{C}_1}}t+\sqrt{\frac{L_{12}}{C_1}}{i}_{12}\left(t_4\right)\sin \frac{1}{\sqrt{L_{12}{C}_1}}t\left(t_4\le t\le t_5\right)(3)$

Assuming T_scr is the minimum recovery time of SCR string, the SCR voltage V_T0 can be expressed as:

$\begin{array}{c}{V}_{T0}=V_{\mathrm{c}1}\left(t\right)-V_{\mathrm{c}2}=V_1-V_1\cos \frac{1}{\sqrt{L_{12}{C}_1}}t+\sqrt{\frac{L_{12}}{C_1}}{i}_{12}\left(t_4\right)\sin \frac{1}{\sqrt{L_{12}{C}_1}}t-V_{clamp2}\le 0\left(t_4\le t\le t_4+T_{\mathrm{s}\mathrm{c}r}\right)\end{array}(4)$

The most important issue of parameter design of the proposed topology is to make sure that the duration of reverse voltage on the SCR string T₀ must be larger than the minimum requested recovery time to make sure the current conducted thought the SCR reach a value below its threshold current and last long enough, thus the thyristor can be switched off reliably.

To meet the minimum recovery time of SCR under the worst situation, and the calculation process can be simplified:

$T_{rv}=\frac{C_1{V}_{C2}}{I_{\max }}\ge \alpha T_{scr}(5)$

The capacitor C₁ and voltage of C₂ can be chosen as:

$\left\{\begin{array}{c}{C}_1\ge \frac{\alpha T_{scr}{I}_{\max }}{V_{C2}}\\ V_{C2}\ge \frac{\alpha T_{scr}{I}_{\max }}{C_1}\end{array}\right.(6)$

Where T_rv is the required reverse voltage time, T_scr is the minimum recovery time of T₀. I_max is the maximum allowed breaking current of SCR-IHCB. α is a redundancy factor and must be larger than 1.

According to Eqs. 5, 6, a larger redundancy factor α increases the reliability of SCR-IHCB, but the capacitor value C₁ and V_c2 becomes larger. A redundancy factor of 1.5∼2 is generally preferred. When the value of α is determined, the value of C₁ and V_C2 should be designed together, A smaller value of C₁ means a faster blocking speed (t_b in Figure 6) of the fault current because V_c1 can rise to V_DC faster, but it also means that a higher V_C2 value is required; a higher V_c2 value also means higher withstand voltage of S₅-S₇, IGBT-in-series or cascaded multi submodule topology can be used, but the cost and loss of the system will also increase. There exists a trade-off between system economy and fault current blocking speed, as shown in Figure 6.

FIGURE 6

FIGURE 6. The relationship between C₁, t_b and V_c2.

3.2 Parameters calculation of MOV

The rated voltage for the MOVs of the typical HCB should be greater than 1.5 times the system voltage to quickly reduce the fault current to zero:

$V_{MOV}\ge 1.5V_{DC}(7)$

The total absorbing energy E_MOV of MOV is associated with the energy storage components of system, which can be given by:

$E_{MOV}=\frac{1}{2}{L}_{DC}{I}_{\max }^2-\frac{1}{2}{C}_1\left(V_{mov}^2-V_{DC}^2\right)(8)$

where L_DC is the value of system equivalent inductance, I_max is the maximum value of fault current.

3.3 Device cost and loss analysis

In order to compare the improvements of the proposed SCR-IHCB, it is compared with the typical HCB+CFC solution which is not integrated (three ABB’s HCB solution (Häfner and Jacobson, 2011) in three lines with one CFC (Sau-Bassols and Gomis-Bellmunt, 2017)) in 10kV/1 kA three-port system, as shown in Figure 7. 4.5 kV IGBT(5SNA1200G452300) and 5.2 kV thyristor(T1451N) are selected in the comparison. The relative conduction loss and device cost of two solutions in the same voltage level are shown in Figure 8, where the ordinate is a relative value and “1” represents the maximum.

FIGURE 7

FIGURE 7. Detailed topologies of two solutions in 10kV/1 kA three-port system (A) Proposed SCR-IHCB; (B) Typical HCB+CFC solution.

FIGURE 8

FIGURE 8. Economic comparison with two solutions in 10 kV three-port system.

As can be seen in Figure 8, the device cost of the proposed solution is much lower than that of typical HCB+CFC solution, because less HCBs are used and large number of fully-controlled semiconductor devices have been replaced by semi-controlled semiconductor devices.

The conduction loss in the proposed SCR-IHCB is much higher in CFC mode, but is lower in bypass mode compared with typical IGBT based HCB + CFC solution. Because in bypass mode, only the conduction loss of LCS is added with the proposed solution, but both conduction loss of IGBTs in LCS and CFC parts are added with the typical solution. Considering the investment and conduction loss in different mode together, the comprehensive cost during operation strongly depends on how often the SCR-IHCB need to operate in CFC mode to ensure stable grid conditions, therefore the comprehensive cost could be much lower than the typical solution in the application scenario where inter line power flow control is only needed occasionally.

4 Modeling and control methodology of CFC

In this section, the dynamic model of the proposed CFC is presented, using averaging technique where the terminals voltages are taken into consideration as setting values. Taking the first scenario for example, and the analysis can be extended to the rest of possible current configurations. We can see the current flow of the first scenario in the Figure 2.

The following set of equations describes the circuit of Figure 2A. This equivalent circuit was developed based on a reduction of the physical circuit layout, where: r_xx and L_xx are the resistance and the inductance of the line xx originated from the CFC bus and carrying an instantaneous current i_x, V_c1 is the capacitor voltage, V₁ is the voltage at the bus where the CFC is connected to, V₂ and V₃ are the voltages at the end terminals of the lines, respectively.

$\left[\begin{array}{ccc}{L}_{12}& 0& 0\\ 0& L_{13}& 0\\ 0& 0& C_1\end{array}\right]\dot{X}=\left[\begin{array}{ccc}-r_{12}& 0& 0\\ 0& -r_{13}& -1\\ 0& 1& 0\end{array}\right]X+\left[\begin{array}{ccc}1& -1& 0\\ 1& 0& -1\\ 0& 0& 0\end{array}\right]U(9)$

$X=\left[\begin{array}{l}{i}_{12}\\ i_{13}\\ V_{c1}\end{array}\right],U=\left[\begin{array}{l}{V}_1\\ V_2\\ V_3\end{array}\right](10)$

Similarly, the state equations of Figure 2B, where the capacitor is discharging into line12, are as follows:

$\left[\begin{array}{ccc}{L}_{12}& 0& 0\\ 0& L_{13}& 0\\ 0& 0& C\end{array}\right]\dot{X}=\left[\begin{array}{ccc}-r_{12}& 0& -1\\ 0& -r_{13}& 0\\ -1& 0& 0\end{array}\right]X+\left[\begin{array}{ccc}1& -1& 0\\ 1& 0& -1\\ 0& 0& 0\end{array}\right]U(11)$

Assume the duty ratio of the charging mode1 is D. Multiplying Eqs. 8, 10 by D and (1−D), respectively, and adding the results to obtain the average model for the CFC for the scenario as follows:

$\left[\begin{array}{ccc}{L}_{12}& 0& 0\\ 0& L_{13}& 0\\ 0& 0& C_1\end{array}\right]\dot{X}=\left[\begin{array}{ccc}-r_{12}& 0& -1+D\\ 0& -r_{13}& -D\\ -1+D& D& 0\end{array}\right]X+\left[\begin{array}{ccc}1& -1& 0\\ 1& 0& -1\\ 0& 0& 0\end{array}\right]U(12)$

At steady state, Eq. 11 can be written as Eq. 12:

$\left[\begin{array}{ccc}-r_{12}& 0& -1+D\\ 0& -r_{13}& -D\\ -1+D& D& 0\end{array}\right]X+\left[\begin{array}{ccc}1& -1& 0\\ 1& 0& -1\\ 0& 0& 0\end{array}\right]U=0(13)$

Solving Eq. 12, the steady-state value of capacitor voltage is obtained as:

$V_c=\frac{\left(V_1-V_2\right)-r_{12}{i}_{12}}{1-D}=\frac{\left(V_1-V_3\right)-r_{12}{i}_{12}}{D}(14)$

Eq. 13 gives an expression for the capacitor voltage as a function of the network parameters and the voltage drops across the cables connected to the CFC which represents the loading condition of the grid.

Given that the power taken from one line is equal to the power added to the other line, the power balancing between state 1 and state 2 as shown in Figure 2 is given by:

$V_{c2\_\mathrm{r}\mathrm{e}\mathrm{f}}\left(1-D\right)I_{12}-V_{c2\_\mathrm{r}\mathrm{e}\mathrm{f}}D{I}_{13}=0(15)$

The relationship between I₁₂ and I₁₃ can be obtained from the above formula:

$\frac{I_{12}}{I_{13}}=\frac{D}{1-D}(16)$

From the previous analysis the voltage ripple can be deduced and it is given by Eq. 16.

$\Delta U=\frac{{DI}_{13}}{C_{2}f}=\frac{\left(1-D\right)I_{12}}{C_{2}f}(17)$

where ƒ is the switching frequency of the CFC.

A block diagram for the control scheme is shown in Figure 9. The control system has two nested PI controllers: an inner capacitor voltage controller and outer DC current controller. The outer controller regulates the DC line current by feeding a reference voltage to the inner voltage controller. The inner controller achieves the required capacitor voltage level by controlling the duty cycle.

FIGURE 9

FIGURE 9. PI controller for CFC mode of SCR-IHCB.

5 MTDC network Simulation Studies

In this section, a simplified three-terminal HVDC system is simulated. As shown in Figure 1, the proposed SCR-IHCB topology is equipped at station 1 to adjust the power of line 12 and line 13. The practical parameter of the three-terminal HVDC system is shown in Table 2.

TABLE 2

TABLE 2. Parameter of three-terminal HVDC system.

The currents flowing from the DC bus of station 1 and the transmission lines in presence of the SCR-IHCB are depicted in Figure 10. The SCR-IHCB operates in the bypass mode for 0 < t < 2s. Thereafter, the CFC changes its operation mode to CFC mode at 2s. Figures 10A, B implies that the SCR-IHCB can adjust the current bidirectionally in CFC mode. The short-circuit fault in line12 happens at time t = 4s. It can be seen in Figures 10A, B that the SCR-IHCB can quickly isolate the fault on line 12, and the transmission between station 1 and station 3 returned to normal (I₁ = I₁₃).

FIGURE 10

FIGURE 10. Performance of SCR-IHCB. (A) Current waveforms with forward power flow. (B) Reverse power flow. (C) Fault current transfer process. (D) Energy absorb by MOV₁. (E) V_T0, V_T1, V_c1 and V_c2. (F) Details of V_T0, V_T1, V_c1 and V_c2. (G) Voltage of transfer branches. (H) Details of voltage of transfer branches. (I) V_S5-V_S8. (J) I_S5-I_S8. (K) V_D1 and V_D2. (L) I_D1 and I_D2.

As shown in Figure 10C, before the fault is detected in t = 4.001s, the SCR-IHCB is still working in CFC mode. when the system detects the fault, IHCB mode is activated, S₅ and S₇ conducts as mentioned above, the fault current goes through T₀, and I_T0 started to rise rapidly. After 2 m (waiting for the UFD₁ completely open), the fault current was successfully transferred to charging path of the capacitor C₁, V_c1 starts to rise (as shown in Figure 10E), in less than 5 m, the fault current (I_c1, I_D1) reaches the peak value 6.1 kA. When V_c1 reaches the protection voltage of MOV₁(250 kV as shown in Figure 10E), the fault current is transferred to MOV path (I_mov1 in Figure 10C) and decreases to zero. The amount of absorbed energy of MOV₁ reaches almost 3.6 MJ as shown in Figure 10D. When the fault current drops to zero, the value of V_T0 return to V_DC-V_c2, and the thyristor T₁ needs to withstand a reverse voltage of V_c1-V_DC, about 50 kV as shown in Figure 10E.

Figure 10F shows that the reverse voltage V_T0 (V_T0 = V_c1 −V_c2) is generated at 4.003s, and the duration time is about 140us, much larger than the minimum requested recovery time of SCR string in (Jamshidi Far and Jovcic, 2018).

Figures 10G, H show the voltage waveform of two transfer branch, LCS₁ and LCS₂ works in CFC mode before fault is detected. UFD₂ and LCS₂ remain on-state to keep transmission of station1 and station 3 after fault blocking, LCS₁ switch off at 4.001s, and the UFD₁ takes 2 m to completely open, then the voltage on UFD₁ increases with V_c1.

Figures 10I, J show the voltage and current of the S₅-S₇. Obviously, the operation sequence of S₅-S₈ is consistent with the theoretical analysis, and the maximum withstand voltage of S₅-S₈ is limited to the given voltage of V_c2, the maximum current is equal to the value when the fault current transferred from T₀ branch to C₁ branch.

Figures 10K, L show that the maximum withstand voltage and current of diode strings (D₁ and D₂) are consistent with the maximum voltage of V_c1 and maximum fault current.

6 Experimental Studies

Considering that the proposed SCR-IHCB topology is a symmetrical structure for fault blocking of two adjacent lines; therefore, the verification for the current opening process of one line is enough. A scale-down prototype is built for verifying the concept of the feasibility of the SCR-IHCB, as shown in Figure 11A, the component marks in Figure 11A are consistent with those in Figure 1A. The diagram of the experimental system is depicted in Figure 11B and the system parameters are listed in Table 3.

FIGURE 11

FIGURE 11. Experimental system. (A) Photograph of the scale down SCR-IHCB prototype. (B) Circuit diagram of three-terminal test platform.

TABLE 3

TABLE 3. Parameters of the experimental system.

6.1 Fault current blocking

The fault blocking waveforms of the SCR-IHCB are shown in Figure 12. It can be seen that after the fault occurs at t₀, after a detection time of 1 m, the IGBT in LCS is turned OFF, fault current is transferred to main breaker branch at t₁. A 2 m delay is set between t₁ and t₂ to simulate the opening time of mechanical switch. The IGBTs in main breaker branch is turned off at t₂, while C₁ is charged and the fault current is successfully interrupted eventually at t₃.

FIGURE 12

FIGURE 12. Measured fault-interrupting waveforms of the DC Fault Mode.

The detailed waveforms of the thyristor T₀ recovery stage is shown in Figure 13. When the value of 220 μF is chosen for C₂, the SCR-IHCB has Δt > 100us as shown in Figure 13A, and the thyristor is turned off successfully, the fault current of the system (I_sys) is quickly transferred from T₀ to T₁ (I_T0 and I_T1 in Figure 13A), the voltage of T₀ (V_T0) rises as C₁ is charged by the system fault current.

FIGURE 13

FIGURE 13. Measured waveforms during the thyristor recovery stage at (A) C₂ = 220μF; (B) C₂ = 100 μF.

When the value of C₂ is reduced to 100 μF, the SCR-IHCB has Δt < 50us, smaller than t_q in datasheet of thyristor SKKT62 which is used in our experiment. It is obvious that the thyristor has failed to turn off, the fault current of the system (I_sys) continues to flow through T₀, Capacitor C₁ and capacitor C₂ are connected in parallel, and the voltage rises synchronously.

6.2 Current control

The CFC function is also verified by experiments, as shown in Figure 14. At the beginning, the current at line 12 (I₁₂) is 12A and at line 13 (I₁₃) is 6A at first. At t = 10 m, the CFC begins to work and the current at line 13 (I₁₃) begins to increase and the current at line 12 (I₁₂) decreases meanwhile. After 5 m, the line current forms a new steady state. It can be found that the controller can keep capacitor voltage constant at 30V (V_c2) during current regulation.

FIGURE 14

FIGURE 14. Measured fault-interrupting waveforms of the current control mode.

7 Conclusion

In this paper, a SCR string and H-bridge module based interline hybrid circuit breaker topology with current flow control function is proposed. The operation principles in normal operation mode and DC fault mode are analyzed, the parameters design principle is also presented in detail. The simulation and experiment results from a meshed HVDC grid model confirm the operational performance of the proposed topology. Compared with other solutions, the topology design is more economical and simpler because only one bidirectional SCR string and only one H-bridge module is needed for two adjacent lines, no additional capacitor pre-charge circuits and inductors are required, the current flow control function is also integrated without additional components.

Data availability statement

The original contributions presented in the study are included in the article/Supplementary Material; further inquiries can be directed to the corresponding author.

Author contributions

QZ: Writing—Original Draft, Experimental Studies and Visualization. JZ: Conceptualization, Methodology and Supervision. XG: Writing—Original Draft and Simulation Studies. QH: Editing, Parameters Design. JY: Process Analysis, Supervision. TW: Supervision.

Funding

This work was supported in part by the National Natural Science Foundation of China under Grant 51607171, in part by The Institute of Electrical Engineering, CAS under Grant E155610301 and E155610201.

Acknowledgments

This is a brief acknowledgement of the contributions of individual colleagues, institutions, or agencies that assisted the writers’ efforts in the writing of this article.

Conflict of interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

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