Cascaded multiplier-free implementation of adaptive anti-jamming filter based on GNSS receiver

Evaluating the computational complexity is critical for assessing the time-domain anti-jamming performance of GNSS receivers. The multiplier is the core component that contributes to the computational complexity in time-domain anti-jamming. However, current algorithms aimed at reducing the complexity of time-domain anti-jamming typically concentrate on shortening the filter length, which fails to address the high computational complexity introduced by the use of multipliers. This paper introduces a cascaded multiplier-free approach for implementing time-domain anti-jamming in navigation receivers. We propose a numerical power decomposition technique based on optimal Canonical Signed Digit coding and coefficient decomposition. By substituting the multiplier with minimal adder and shift operations, the computational complexity of the anti-jamming filter with a high quantization bit-width can be considerably decreased. An optimization strategy is presented, and the low-complexity multiplier-free technique is applied to the time-domain anti-jamming filter. Compared to the traditional Canonical Signed Digit multiplier-free technique, our method can reduce the components required for a 12-bit quantization anti-interference filter by one adder, 20 shift operations, and five coded word lengths, while maintaining a pseudo-range measurement deviation below 0.27 ns.

1 Introduction

The Global Navigation Satellite System (GNSS) offers precise spatial and temporal reference data, including three-dimensional positioning, velocity, and timing [1]. Due to the substantial distance between the satellites and the ground, and the limited satellite resources, the navigation signal is susceptible to being overwhelmed by jamming [2]. As various electronic systems have advanced, competition for electromagnetic frequency bands has become intense, leading to severe jamming [3]. Ensuring anti-jamming capabilities for GNSS receivers is crucial to navigate through complex electromagnetic and electronic warfare environments, ensuring the accuracy of positioning, navigation, and timing for navigational terminals [4].

Given the spectrum overlap, mutual interference occurs between satellite navigation, radar, and 5G systems [5]. The low cost of time-domain anti-jamming makes it a prevalent solution for fixed-band narrowband jamming suppression, and is crucial for assessing GNSS receiver performance. Researchers are developing cost-effective navigation receivers to keep pace with the evolving GNSS systems and the development of new features. Chien [6] presents a cost-effective cascaded IIR adaptive notch filter for interference suppression that significantly reduces complex computations resulting from Fourier Transforms (FFT), inverse FFT, or wavelet transformations. Ren et al. [7] proposes a subspace projection algorithm with a brief projection length for continuous wave and linear frequency-sweep interference, thereby reducing computational complexity. Wang et al. [8] introduces an adaptive narrowband interference (NBI) suppression technique utilizing coded-aid technology that obviates the need for FFT or matrix inversion. Additionally, variable tap-length LMS and sparse algorithms have seen extensive development [9–11]. Nonetheless, the multiplier continues to impact complexity. The multiplier is a pivotal component of DSP calculations within the navigation receiver [12]. Its complexity scales quadratically with the quantization bit width, thus necessitating considerable computational resources. Because multiplication operations influence the jamming suppression performance in hardware, a multiplier-less implementation has been adopted to reduce costs and accelerate convergence [13, 14].

Multiplier-less implementation replaces multipliers with other operations, such as the read-only memory (ROM) lookup table, distributed arithmetic (DA) algorithm, binary complement, Coordinate Rotation Digital Computer (CORDIC), multiple constant multiplication (MCM), and canonic signed digit (CSD) coding [15–17]. CSD coding components the filter coefficient as the sum or difference of the power of 2, replacing the multiplier by shift operation and adder [18]. The coefficient decomposition decomposes the coefficient into the product of several numbers by the lookup table, reducing the adder number by cascading. Methods can be used in conjunction to reduce the adder number and sampling bit width. There have been optimization studies on the implementation methods of various filters without multipliers [19–21].

However, the above multiplier-less implementation methods are limited in the practical GNSS receiver applications, which are usually used in fixed-coefficient filters. The anti-jamming filter coefficient of GNSS receivers is usually considerable, while the existing multiplication-less implementation scheme is limited by the quantization bit width, resulting in significant quantization errors. The anti-jamming filter multiplication-less implementation method should be further optimized to minimal adders and shift operations with easy implementation.

Building on previous work, this paper proposes a cascaded multiplier-free implementation method for GNSS receiver time-domain anti-jamming filters. This method is applied to the static time-domain anti-jamming of satellite navigation receivers, optimizing the design of high-gain filter coefficients without multipliers. It reduces the number of adders, shift operations, and the coding word length of filter coefficients, thereby decreasing the computational complexity of the anti-jamming filters.

2 System model

2.1 GNSS receiver model

The GNSS system consists of the space segment, ground segment, and user segment. Figure 1 illustrates the GNSS receiver structure. The user terminals process the received radio frequency (RF) signals in RF front-end (RFFE). The baseband digital signal processing (DSP) suppresses the unexpected interference after the digital down conversion (DDC), and applies the multiplier-free anti-jamming filter based on the LMS adaptive algorithm. After the anti-jamming data is captured and tracked, it finally enters terminal’s back-end (BE) for realizing positioning, navigation and timing (PNT) functions [22].

Figure 1

Figure 1. GNSS receiver structure.

Satellite navigation signals include the carrier, pseudo-random (PRN) code, and message data. The satellite navigation signal can be expressed by the carrier modulated with the spread spectrum signal of PRN code and data in Eq. 1:

$s\left(t\right)=\sum \sqrt{2P_t}\left(x\left(t\right)D\left(t\right)\right)\sin \left(2\pi ft+\theta \right)(1)$

where, $P_t$ is the average power of navigation signal, $x\left(t\right)$ is the PRN code level, $D\left(t\right)$ is the satellite broadcast message data, $f$ is the central frequency of RF signal, $\theta$ is the initial phase of the carrier.

Suppose that the receiver thermal noise is $u\left[n\right]$, the interference signal is $j\left[n\right]$, such as continuous wave interference or narrowband Gaussian noise interference. Continuous wave interference (CWI) aims at the central frequency of satellite navigation signals by the continuous high-power single-frequency signal [23]. Narrowband interference (NBI) is generated by band-limited Gaussian white noise [24]. The CWI and NBI can be expressed as Eqs 2, 3 respectively:

$J_{\text{CWI}}=\sqrt{2P_J}\cos \left(2\pi f_{J}t+{\phi }_0\right)(2)$

$J_{\text{NBI}}=A_{n}G\left(t\right)\ast Sa\left(t\right)(3)$

where, $P_J$ is the interference power, $f_J$ is the interference frequency, ${\phi }_0$ is the initial phase, $A_n$ is the narrowband interference amplitude, $G\left(t\right)$ is the Gaussian white noise, $G\left(t\right)$ is convoluted with the finite band-pass gate function $Sa\left(t\right)$ to generate narrowband interference.

The resultant input signal before the anti-jamming module can be expressed in Eq. 4 [25]:

$x\left[n\right]=s\left[n\right]+j\left[n\right]+u\left[n\right](4)$

2.2 Multiplier-free time-domain adaptive anti-jamming model

The time-domain anti-jamming algorithm utilizes the adaptive filter to suppress interference. The iterated filter coefficients should be implemented to be multiplier-free and then assigned to the weight storage module. Figure 2 illustrates the flow chart of the multiplier-free time-domain adaptive anti-jamming algorithm.

Figure 2

Figure 2. Anti-jamming flow chart with multiplier-free implementation.

Suppose that the input vector of the $N$-long filter at time $n$ is as Eq. 5:

$\mathbf{x}={\left[x\left(n\right),x\left(n-1\right),\cdots ,x\left(n-N+1\right)\right]}^{\mathrm{T}}(5)$

Suppose the filter quantization bit width is L. The filter weight vector is as Eq. 6:

$\mathbf{W}=\text{fix}\left[\text{Norm}\left[{\omega }_1,{\omega }_2,...,{\omega }_N\right]\cdot 2^L\right]=\left[w_1,w_2,...,w_N\right](6)$

where, $\text{fix}\left[\cdot \right]$ is the rounding function to round off the input signal, $\text{Norm}\left[\cdot \right]$ is the normalized function.

Define the multiplier-free implementation method as $\mathrm{\Phi }\left[\cdot \right]$. With the iterated coefficients implemented multiplier-free, the anti-jamming output signal can be expressed as:

$y\left(n\right)=\mathbf{x}\cdot \mathbf{W}={\displaystyle \sum _{k=1}^N}x\left(n-k+1\right)\mathrm{\Phi }\left[w_k\right](7)$

The error signal $e\left(n\right)$ is defined as the difference between the anti-jamming output signal $y\left(n\right)$ and the desired signal $d\left(n\right)$, where the desired signal is generally considered to be navigational signal, as shown in Eq. 8:

$e\left(n\right)=d\left(n\right)-y\left(n\right)\approx s\left(n\right)-y\left(n\right)(8)$

The iterative formula of LMS algorithm can be expressed as Eq. 9 [26]:

${\mathbf{W}}_M^{n+1}={\mathbf{W}}_M^n+\mu {\mathbf{x}}^{\ast }\left(n\right)e\left(n\right)={\mathbf{W}}_M^n+\mu {\mathbf{x}}^{\ast }\left(n\right)\left[s\left(n\right)-y\left(n\right)\right]\approx {\mathbf{W}}_M^n-\mu {\mathbf{x}}^{\ast }\left(n\right)y\left(n\right)(9)$

where ${\left[\cdot \right]}^{\ast }$ represent the conjugation.

The multiplier-free implementation of GNSS time-domain anti-jamming is applicable to satellite navigation receivers with limited hardware resources. For instance, mobile phones require the development of miniaturization capabilities and maintaining anti-interference capabilities, and spaceborne receivers’ functionality is expanded within the constraints of limited resources. Figure 3 depicts a ground-test module of a satellite-borne receiver in its practical application.

Figure 3

Figure 3. Practical application: ground-test module of spaceborne receiver. (A) Ground testing architecture. (B) Hardware development board.

3 Problem formulation

3.1 CSD coding

The signed number is one of the essential non-standard fixed-point number in computer algorithm implementation, and its digital range is $\left\{1,0\right\}$. Since it is not unique, the system with the least nonzero elements is called the regular signed digit system.

The CSD coding expresses the filter coefficients as the sum or difference of the power of 2, which is realized by shift operation and adder. The optimal CSD coding can also reduce the adder number and the maximum encoding lord length [27].

The mathematical expression of the FIR-filter anti-jamming can be simplified as shown in Eq. 10 [28]:

$y_i={\displaystyle \sum _{i=0}^{N-1}}{h}_i{x}_i={\displaystyle \sum _{i=0}^{N-1}}{x}_i{\displaystyle \sum _{j=0}^{M-1}}{h}_i\left(j\right)={\displaystyle \sum _{i=0}^{N-1}}{x}_i\left(2^{M-1}{h}_i\left(M-1\right)+2^{M-1}{h}_i\left(M-1\right)+\cdots +2^1{h}_i\left(1\right)+2^0{h}_i\left(0\right)\right)(10)$

where, $h_i$ represents the $i-th$ weight of the filter, $x_i$ is the input data to the $i-th$ weight, $h_i\left(j\right)=0,1,-1$ represents the binary representation of the $i-th$ weight, $M$ is the binary bit length.

CSD coding replaces all 1 sequences greater than 2 with $10...0\overline{1}$ from the lowest bit, where $\overline{1}$ represents the negative 1 bit. The best CSD coding has minor nonzero elements and the least subtraction times. Starting from the highest significant bit, replace $10\overline{1}$ with $011$ [29].

Suppose that the word length of the binary complement-on-two of value $\omega$ is $L_{\text{bin}}$ then the Binary expression is as Eq. 11:

$A_{\text{bin}}={a^{″}}_{L_{\text{bin}}-1}{a^{″}}_{L_{\text{bin}}-2}\cdots a_1^{″}{a}_0^{″}(11)$

where, $a_i=0,1,i=0,1,...,L_{\text{bin}}-1$

The word length of CSD encoding of value A is $L_{\text{CSD}}$ then the CSD expression is as Eq. 12:

$A_{\text{CSD}}={a^{\prime }}_{L_{\text{CSD}}-1}{a^{\prime }}_{L_{\text{CSD}}-2}\cdots a_1^{\prime }{a}_0^{\prime }(12)$

where, $a_j^{\prime }=-1,0,1,j=0,1,...,L_{\text{CSD}}-1$. Usually, the relationship between CSD code word length and binary complement word length is as shown in Eq. 13:

$L_{\text{CSD}}=L_{\text{bin}}\left(+1\right)(13)$

The binary complement is updated to CSD coding as shown from Eqs 14–16:

${\theta }_i=a_i\wedge a_{i-1}(14)$

${\zeta }_i={\overline{\zeta }}_{i-1}{\theta }_i(15)$

$a_j^{\prime }=\left(1-2a_{i+1}\right){\zeta }_i(16)$

where, ${\left[\cdot \right]}^{\wedge }$ is the exclusive OR operation, the initial value can be expressed as $a_{i-1}=0,{\zeta }_{i-1}=0,a_n=a_{n-1}$.

Then optimize the CSD coding that may have storage waste by Eq. 17:

$A=a_{L-1}{a}_{L-2}\cdots a_1{a}_0(17)$

where, $a_k=-1,0,1,k=0,1,...,L-1$. Usually, the relationship between CSD code word length and binary complement word length is as shown in Eq. 18:

$L=L_{\text{CSD}}\left(-1\right)(18)$

Its update process can be expressed from Eqs 19–21:

$a_k=\text{ceil}\left(\frac{a_j^{\prime }+a_{j-2}^{\prime }}{2}\right)(19)$

$a_{k-1}=a_j^{\prime }\oplus a_k(20)$

$a_{k-2}=\left[1-2\left(a_{j-1}^{\prime }\oplus a_{k-1}\right)\right]a_{j-2}^{\prime }(21)$

where, $\oplus$ is the logical AND operation.

The number of adders is expressed as Eq. 22:

$S_{\text{add}}={\displaystyle \sum _{k=0}^{n-1}}\left|a_k\right|-1(22)$

The number of shift operations is expressed as Eq. 23:

$S_{\text{shift}}={\displaystyle \sum _{k=0}^{n-1}}{\left.k\right|}_{\left|a_k\right|=1}(23)$

The figure shows the best CSD coding schematic. The value 211 is taken as an example in Figure 4, the multiplier-free design based on the optimal CSD coding is composed of 5 values of the power of 2, and the multiplication operation is realized by four adders and 18 shift operations.

Figure 4

Figure 4. Optimal CSD coding schematic.

3.2 Numerical power decomposition

Numerical power decomposition is achieved by cascading several values to reduce the hardware cost of multiplier-less implementation [30]. For example, the traditional binary encoding of the value 231 is ${11100111}_{\text{bin}}$, the best CSD encoding is $100\overline{1}0100\overline{1}$, and the original multiplier implementation can be reduced from 5 adders to 3. If 231 is factorized into the $7\times 33$ cascade, the adders’ number can be reduced to 2. Figure 5 is the example diagram of numerical power decomposition.

Figure 5

Figure 5. Numerical power decomposition schematic.

The value $\omega$ can be decomposed into the product of $\mathrm{\Theta }$ values and realized by cascading [31] as shown in Eq. 24:

$\omega ={\mathrm{\Omega }}_1{\mathrm{\Omega }}_2\cdots {\mathrm{\Omega }}_{\mathrm{\Theta }}(24)$

where, ${\mathrm{\Omega }}_p$ is the $p$-th power factor, which consists of the addition and subtraction of the power of 2 as shown in Eq. 25:

${\mathrm{\Omega }}_p=2^{k_1}\pm \cdots \pm 2^{k_2}(25)$

The numerical value will affect the device cost of the filter. The total adder number can be expressed as the sum of the number of adders required for different decomposition factors, as shown from Eqs 26–28:

$N_{\text{add}}={\displaystyle \sum _{p=1}^{\mathrm{\Theta }}}{S}_{\text{add}}^p(26)$

$N_{\text{shift}}={\displaystyle \sum _{p=1}^{\mathrm{\Theta }}}{S}_{\text{shif}t}^p(27)$

$N_{\text{bit}}=\max L_p(28)$

where, $S_{\text{add}}^p$, $S_{\text{shif}t}^p,L_p$ are the number of adders, the number of shift operations, and the maximum word length required for the optimal CSD encoding of the decomposition factor ${\mathrm{\Omega }}_p$, respectively.

3.3 Motivations and optimization object

Static anti-jamming filters are usually used in power-sensitive terminals, and computational complexity is one of the most critical design elements. The effect of CSD optimal coding to reduce complexity is limited, and the existing numerical power decomposition is mainly the lookup table method. The accessible decomposition results are limited, creating difficulties for the multiplier-less implementation of large values.

Based on the disadvantages of optimal CSD coding and coefficient decomposition, in order to solve the problem of high gain in the actual filter coefficients, this paper proposes a cascaded multiplier-less implementation. The multiplier-less filter is implemented with minimum adders, reducing the shift operation and memory word length. The optimization objective is shown in Eq. 29:

$\text{minimize }{N}_{\text{add}}\begin{array}{cc}& \text{subject\hspace{0.17em}to}\left\{\begin{array}{c}{N}_{\text{add}}\le S_{\text{add}}\\ N_{\text{shift}}\le S_{\text{shift}}\\ N_{\text{bit}}\le L\end{array}\right.\end{array}(29)$

4 Proposed approach

To design a multiplier-less anti-jamming filter, the numerical power decomposition of the filter coefficients is first performed to obtain each decomposition factor. The multiplier-less coding of all decomposition factors is designed according to the optimal CSD coding method. The flowchart is shown in Figure 6.

Figure 6

Figure 6. Cascaded multiplier-free implementation method flowchart.

Firstly, the numerical power decomposition of the filter coefficient $w_i$ is carried out, and four kinds of decomposition factors are obtained. The decomposition matrix can be expressed as is shown in Eq. 30:

$\mathrm{{\rm P}}=\left[\begin{array}{cccc}{\mathrm{{\rm P}}}_1& {\mathrm{{\rm P}}}_2& {\mathrm{{\rm P}}}_3& {\mathrm{{\rm P}}}_4\end{array}\right](30)$

where, ${\mathrm{{\rm P}}}_i$ is the i-th decomposition factor:

Assume that $2^j$ is a zero-order power factor ${\mathrm{\Upsilon }}_0^j$, and the first type of decomposition factor ${\mathrm{{\rm P}}}_1$ is the divisor ${\mathrm{\Upsilon }}_0^j$ that can divide $w_i$ at most. Divide $w_i$ by ${\mathrm{{\rm P}}}_1$ to get $w_i^1$, as shown in Eqs 31, 32:

${\mathrm{P}}_1=\max \left({\mathrm{\Upsilon }}_0^j\left|\mathrm{mod}\left(w_i,{\mathrm{\Upsilon }}_0^j\right)=0\right.\right),\begin{array}{cc}& j=1,2,...,\text{floor}\left(\frac{B}{2}\right)\end{array}(31)$

$w_i^1=w_i/{\mathrm{P}}_1(32)$

where, $\mathrm{mod}\left(\cdot \right)$ is the residue function, $B$ is the binary length of $w_i$, and $\text{floor}\left(\cdot \right)$ is the down-integer function. The cascade of the first type of decomposition factor is realized by a $j$-th forward shift operation.

Assume that $2^l+1$ or $2^l-1$ is a one-order power factor ${\mathrm{\Upsilon }}_1^j$, the second decomposition factor ${\mathrm{{\rm P}}}_2$ is the divisor ${\mathrm{\Upsilon }}_1^j$ that can divide ${w_i}^{\prime }$ at most. Divide $w_i^1$ by ${\mathrm{{\rm P}}}_2$ to get $w_i^2$ as shown in Eqs 33, 34:

${\mathrm{P}}_2=\max \left({\mathrm{\Upsilon }}_1^j\left|\mathrm{mod}\left(w_i^1,{\mathrm{\Upsilon }}_1^j\right)=0\right.\right),\begin{array}{cc}& j=1,2,...,\text{floor}\left(\frac{B^{\prime }}{2}\right)\end{array}(33)$

$w_i^2=w_i^1/\mathrm{\Pi }{\mathrm{\Upsilon }}_1^j(34)$

where, $B^{\prime }$ is the binary length of $w_i^1$. The second decomposition factor ${\mathrm{{\rm P}}}_2$ is realized by an l-bit forward shift operation and an adder.

Assume that $2^m+2^n+1$ or $2^m+2^n-1$ or $2^m-2^n+1$ or $2^m-2^n-1$ is the second-order power factor ${\mathrm{\Upsilon }}_2^j,$ The third decomposition factor ${\mathrm{{\rm P}}}_3$ is the divisor ${\mathrm{\Upsilon }}_2^j$ that can divide $w_i^2$ at most. Devide $w_i^2$ by ${\mathrm{{\rm P}}}_3$ to get ${\mathrm{\Upsilon }}_2^j$, as shown in Eqs 35, 36:

${\mathrm{P}}_3=\max \left({\mathrm{\Upsilon }}_2^j\left|\mathrm{mod}\left(w_i^2,{\mathrm{\Upsilon }}_2^j\right)=0\right.\right),\begin{array}{cc}& m,n=1,2,...,\text{floor}\left(\frac{B^{″}}{2}\right)\end{array}(35)$

$w_i^3=w_i^2/\mathrm{\Pi }{\mathrm{\Upsilon }}_2^j(36)$

where, $B^{″}$ is the binary length of $w_i^2$. The third type of decomposition factor is realized by 1 m displacement bit operation, 1 n displacement bit operation and 2 adders.

The fourth decomposition factor ${\mathrm{{\rm P}}}_4$ is the remainder $w_i^3$ divided by the third decomposition factor as shown in Eq. 37:

${\mathrm{{\rm P}}}_4=w_i^3(37)$

Define the multiplier-free implementation matrix is a cellular matrix as Eq. 38:

$\mathrm{\Theta }=\left\{\begin{array}{cccc}\left[\begin{array}{c}{a}_{1,B_1}\\ a_{1,B_2}\\ ⋮\\ a_{1,B_{M_1}}\end{array}\right]& \left[\begin{array}{c}{a}_{2,B_1}\\ a_{2,B_2}\\ ⋮\\ a_{2,B_{M_2}}\end{array}\right]& \left[\begin{array}{c}{a}_{3,B_1}\\ a_{3,B_2}\\ ⋮\\ a_{3,B_{M_3}}\end{array}\right]& \left[\begin{array}{c}{a}_{4,B_1}\\ a_{4,B_2}\\ ⋮\\ a_{4,B_{M_4}}\end{array}\right]\end{array}\right\}(38)$

Based on complexity, a better multiplier-free implementation method is selected. In the decomposition process of any power factor ${\mathrm{P}}_p$, it should be ensured that the cumulative number of adders and the cumulative number of shift operations do not exceed the total number of CSD codes, as shown in Eqs 39, 40:

${\displaystyle \sum _{p=1}^{\mathrm{\Lambda }}}{S}_{\text{add}}^p\le S_{\text{add}}(39)$

${\displaystyle \sum _{p=1}^{\mathrm{\Lambda }}}{S}_{\text{shift}}^p\le S_{\text{shift}}(40)$

When Eqs 39, 40 is violated in any numerical power decomposition process, the numerical decomposition should be stopped. The decomposition process takes the last decomposition factor as the penultimate factor, and the remainder divided by the penultimate factor is recorded as the last factor. When the complexity of the cascaded multiplier-less implementation is higher than that of the traditional optimal CSD coding, the optimal CSD coding method is still used to achieve multiplication-free coefficients.

According to Eqs 7, 38, the logic circuit flow of anti-jamming output signal is derived in Eq. 41:

$y\left(n\right)={\displaystyle \sum _{k=1}^N}{\displaystyle \prod _{i=1}^4}{\displaystyle \sum _{j=1}^{M_i}}x\left(n-k+1\right)\cdot 2^{B_j}(41)$

5 Performance analysis

5.1 Algorithm complexity comparison

Table 1 presents the complexity comparison between the proposed method and the traditional multiplier-free implementation method, considering the number of adders, shift operations, and maximum word length. The table displays the number of devices for various values under both multiplier-free implementation methods, highlighting the less complex approach. Compared to the traditional optimal CSD coding, the proposed method significantly reduces complexity in multiplier-free implementation. The number of adders is reduced by 0 or 1, while the number of shift operations and the maximum word length are reduced significantly by 13 and 2, respectively.

Table 1

Table 1. Algorithm complexity comparison.

In order to verify the universal adaptability of the cascaded multiplier-less algorithm, the application rate and complexity optimization performance of the new algorithm with 1∼1,000 values is analyzed, respectively. Figure 7A shows the usage proportion of the proposed method. The total integer value of the coefficient is 1∼1,000, the smoothing point is set to 500, and the percentage of the cascade multiplier-less implementation is selected for each 400-point data calculation optimization method. The results show that as the coefficient increases, the optimization effect of the cascaded multiplier-less implementation method is better. Figure 7B demonstrates the smoothing result of the device reduction after using the proposed algorithm. Since the device complexity optimization results are relatively scattered, 59 is used as the smoothing unit to smooth the optimization data of adder, shift operation, and maximum coding word length, respectively. The results show that the cascade multiplier-free implementation method significantly reduces the number of the three devices on the graph. Among them, the number of shift operations decreases the most, and the maximum reduction reaches 19.

Figure 7

Figure 7. Universal adaptability analysis. (A) Usage proportion of the proposed method. (B) Complexity optimization performance.

The digital filters with lengths of 31 and 59 are designed by software. The filter quantization bit width is 12, and the initially designed filter is quantized. The optimization effect of the proposed method on the device complexity is verified based on the designed anti-jamming filter to ensure the effectiveness of the cascaded multiplier-free method in the GNSS receiver. Figure 8 shows that the optimal CSD coding method based on cascaded multiplier-free implementation reduces the multiplier and shift operations compared with CSD coding. After filter coefficient decomposition, the number of adders optimized by CSD coding is reduced by 0–2, and the shift operation is reduced by 0–5.

Figure 8

Figure 8. Complexity optimization comparison of different CSD codes based on factor cascade. (A) 30-order filter. (B) 58-order filter.

Figure 9 compares the anti-jamming filter complexity based on the cascaded multiplier-free implementation and the traditional method to verify the method availability. The results show that the adder reduction of the proposed method is greater than 0 compared with the traditional method, and the complexity reduction of the shift operation and the maximum code length is more pronounced. When the middle tap coefficient of the 58-order filter is 1,024, the number of shift operations is reduced by 20, and the maximum code length is reduced by 5.

Figure 9

Figure 9. Comparison of device count between the proposed and traditional multiplier-free method. (A) 30-order filter. (B) 58-order filter.

Debugging and verification were performed on the test platform illustrated in Figure 3. By minimizing the number of effective operations, cascading multiplication-free processing was applied to the constant multiplier. The anti-jamming module achieved a 52% reduction in its effective circuit area.

5.2 Anti-jamming performance

The carrier-to-noise ratio (CNR) after interference mitigation is a quantitative assessment metric for evaluating time-domain interference resistance [32]. It is defined as the ratio of the carrier power to the power spectral density of the baseband signal noise. A too low carrier-to-noise ratio can severely affect the receiver’s ability to correctly capture and track. Carrier-to-noise ratio loss is the difference between the carrier-to-noise ratio under no-interference conditions and the carrier-to-noise ratio after interference mitigation defiened as Eq. 42.

$\Delta CNR={\left[C/N\right]}_0-{\left[C/N\right]}_{\text{ajm}}=10\lg \left\{\frac{B_n\cdot {\int }_{-\infty }^{\infty }{S}_s\left(f\right)df\cdot \left({\int }_{-\infty }^{\infty }{S}_y\left(f\right)df-{\int }_{-\infty }^{\infty }{\left|H\left(f\right)\right|}^2{S}_s\left(f\right)df\right)}{{\int }_{-\infty }^{\infty }{S}_n\left(f\right)df\cdot {\int }_{-\infty }^{\infty }{\left|H\left(f\right)\right|}^2{S}_s\left(f\right)df}\right\}(42)$

Where, $S_s\left(f\right)$, $S_n\left(f\right)$ and $S_y\left(f\right)$ are the power spectral densities of navigation signal, noise signal and anti-interference signal respectively, $H\left(f\right)$ is the filter frequency response, and $B_n$ is the noise bandwidth.

A static filter with the navigation signal frequency as the stopband center frequency is designed, and the filter quantization bit width is set to 12. The carrier-to-noise ratio (CNR) of the BD3 signal is set to 50 dB·Hz, the interference bandwidth is 2MHz, the jamming-to-signal ratio (JSR) is 40dB, and the sampling rate of the software receiver is 25 MHz. The narrowband interference suppression performance based on the BD3 signal is shown in Figure 10. Figure 10A shows the spectrum before and after anti-jamming. The results show that the cascaded multiplier-free method can achieve anti-interference. The adaptive filter forms a null at least 30 dB in the interference frequency band. Figure 10B shows the navigation signal CNR after suppressing interference. The maximum CNR loss is less than 2 dB·Hz.

Figure 10

Figure 10. Interference suppression performance. (A) Spectrum diagram before and after anti-jamming. (B) Anti-jamming output CNR.

Figure 11 analyzes the ranging accuracy of the cascaded multiplication-free anti-interference method. Figure 11A displays the correlation function between the anti-interference output and the local signals. By observing the 10 chips surrounding the correlation peak, the correlation function of the output signal remains symmetric with the local signal, and the correlation peak position shows no obvious distortion. Figure 11B measures the symmetry of the correlation peak by the SCB curve bias and quantitatively analyzes the ranging deviation of the receiver [30]. Control the convergence step to reduce the influence of the time-varying filter on the ranging accuracy. Under a 31-order anti-interference filter, the pseudo-range measurement deviation is kept within 0.27 ns, which can ensure the ranging accuracy.

Figure 11

Figure 11. Measurement accuracy analysis. (A) The correlation function of the output and local signals. (B) SCB curve bias.

6 Conclusion

This paper introduces a cascaded multiplier-free implementation method and enhances the corresponding implementation scheme. This method is applied to the static time domain anti-jamming of GNSS receivers by replacing multipliers with a minimal number of adders and shift operations, utilizing optimal CSD coding and numerical power decomposition. Simulation results demonstrate that interference occupying 20% of the navigation signal bandwidth can be effectively suppressed, optimizing the anti-jamming filter structure. The number of adders, shift operations, and maximum code length are significantly reduced, with the maximum number of shift operations decreased by 20. The pseudo-range measurement accuracy has been verified to be within 0.27 ns, ensuring adequate ranging performance.

Data availability statement

The raw data supporting the conclusion of this article will be made available by the authors, without undue reservation.

Author contributions

JS: Writing–review and editing, Writing–original draft, Software, Methodology, Data curation. LC: Writing–review and editing, Writing–original draft, Methodology, Conceptualization. ZuL: Writing–review and editing, Methodology, Investigation, Funding acquisition, Conceptualization. BL: Writing–review and editing, Supervision, Investigation. ZhL: Writing–review and editing, Supervision, Formal Analysis, Data curation. ZX: Writing–review and editing, Visualization, Supervision, Software. GS: Writing–review and editing, Supervision, Resources, Project administration. WL: Writing–review and editing, Supervision, Resources, Investigation.

Funding

The authors declare that financial support was received for the research, authorship, and/or publication of this article. This research was funded by the National Natural Science Foundation of China (No. 62003354).

Acknowledgments

The authors would like to thank the editors and reviewers for their efforts to help the publication of this paper.

Conflict of interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

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