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ORIGINAL RESEARCH article

Front. Neurosci.
Sec. Neuromorphic Engineering
Volume 18 - 2024 | doi: 10.3389/fnins.2024.1425861
This article is part of the Research Topic From Theory to Practice: The Latest Developments in Neuromorphic Computing Applications View all 3 articles

Real-Time Execution of SNN Models with Synaptic Plasticity for Handwritten Digit Recognition on SIMD Hardware

Provisionally accepted
Bernardo Vallejo-Mancero Bernardo Vallejo-Mancero 1*Jordi Madrenas Jordi Madrenas 1Mireya Zapata Mireya Zapata 2
  • 1 Departament d'Enginyeria Electronica, Universitat Politecnica de Catalunya, Barcelona, Catalonia, Spain
  • 2 Centro de Investigación en Mecatrónica y Sistemas Interactivos - MIST, Universidad Indoamérica, Quito, Ecuador

The final, formatted version of the article will be published soon.

    Recent advancements in neuromorphic computing have led to the development of hardware architectures inspired by Spiking Neural Networks (SNNs) to emulate the efficiency and parallel processing capabilities of the human brain. This work focuses on testing the HEENS architecture, specifically designed for high parallel processing and biological realism in SNN emulation, implemented on a ZYNQ family FPGA. The study applies this architecture to the classification of digits using the well-known MNIST database. The image resolutions were adjusted to match HEENS' processing capacity. Results were compared with existing work, demonstrating HEENS' performance comparable to other solutions. This study highlights the importance of balancing accuracy and efficiency in the execution of applications. HEENS offers a flexible solution for SNN emulation, allowing for the implementation of programmable neural and synaptic models. It encourages the exploration of novel algorithms and network architectures, providing an alternative for real-time processing with efficient energy consumption.

    Keywords: HEENS, neuromorphic hardware, Spiking Neural network, LIF model, Spike Timing Dependent Plasticity, Mnist dataset, Homeostasis, FPGA

    Received: 30 Apr 2024; Accepted: 22 Jul 2024.

    Copyright: © 2024 Vallejo-Mancero, Madrenas and Zapata. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

    * Correspondence: Bernardo Vallejo-Mancero, Departament d'Enginyeria Electronica, Universitat Politecnica de Catalunya, Barcelona, 08034, Catalonia, Spain

    Disclaimer: All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article or claim that may be made by its manufacturer is not guaranteed or endorsed by the publisher.