Rethinking 1T1R Architecture and OxRAM Stack for Memristive Neural Network Inference In-Memory

Joel Minguet Lopez ^* Sylvain Barraud David Cooper Audrey Jannaud Adeline Grenier Aurélie Souhaité Jean-Michel Pedini Corinne Comboroure Ahmed Gharbi François Boulard Clément Castan Amélie Lambert François Andrieu

• CEA Grenoble, Grenoble, France

Neural Network hardware in-memory implementations based on memristive synapses are a promising path towards energy efficient Edge computing. Among others, Oxide-based Resistive Random Access Memory (OxRAMs) devices utilization for synaptic weight hardware implementation has shown promising performance on various types of Neural Networks, notably when coupled with bit-error correcting codes or adaptive programming schemes for the device intrinsic variability management. In this context, memristive footprint reduction coupling with Multi-Level-Cell (MLC) operation remains essential to hardware implement highly accurate state-of-art Neural Networks, whose number of parameters is exponentially increasing over time. In this work, a compact OxRAM-based 1 Transistor – 1 Resistor (1T1R) architecture, where the memory is integrated inside the 40nm×40nm drain contact of thin-gate oxide FDSOI transistors, is demonstrated in 28nm technology. The memory structure is optimized from the OxRAM active material level to the cell architecture. This results in 106 endurance and 11-level MLC encoding resilient to 109 inference cycles compatible with 0.0357μm2 bitcell footprint potential in 28nm technology. Altogether, the proposed 1T1R cell density is competitive with respect to ultra-dense 1S1R-based Crossbar arrays, while being compatible with in-memory Neural Network inference implementations on-chip.