AUTHOR=Lai Wei-Ting , Yang Kuo-Ching , Liao Po-Hsiang , George Tom , Li Pei-Wen 

TITLE=Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

JOURNAL=Frontiers in Materials

VOLUME=3

YEAR=2016

URL=https://www.frontiersin.org/journals/materials/articles/10.3389/fmats.2016.00005

DOI=10.3389/fmats.2016.00005

ISSN=2296-8016

ABSTRACT=<p>We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO<sub>2</sub>/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si<sub>3</sub>N<sub>4</sub> buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5–90 nm), the SiO<sub>2</sub> thickness (3–4 nm), and the SiGe-shell thickness (2–15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO<sub>2</sub>/Ge-dot and SiO<sub>2</sub>/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO<sub>2</sub>/SiGe and Al/SiO<sub>2</sub>/Ge-dot/SiO<sub>2</sub>/SiGe MOS capacitors exhibit low interface trap densities of as low as 3–5 × 10<sup>11</sup> cm<sup>−2</sup> eV<sup>−1</sup> and fixed charge densities of 1–5 × 10<sup>11</sup> cm<sup>−2</sup>, suggesting good-quality SiO<sub>2</sub>/SiGe-shell and SiO<sub>2</sub>/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si<sub>1−</sub><italic><sub><bold><italic>x</italic></bold></sub></italic>Ge<italic><sub><bold><italic>x</italic></bold></sub></italic> shell (<italic>x</italic> &gt; 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.</p>