A Three-Input Central Capacitor Converter for a High-Voltage PV System

High-voltage photovoltaic (PV) techniques have their own advantages in PV plants for reducing the construction cost and improving the operational efficiency. However, the high input PV voltage increases the mismatch losses of PV arrays, which is also a key factor that influences the energy yield of PV plants. This paper proposes a three-input central capacitor (TICC) dc/dc converter for a high-voltage PV system, where four low-rating cascaded buck-boost converters connect to the series-connected three low-voltage PV arrays and two capacitors and realize the maximum power point tracking independently. Meanwhile, there is a neutral point in the proposed converter, enabling it to be connected with the rear-end three-level inverter directly. It can also help balance the three-level dc-link voltage by properly regulating the transferred energy among three input sources. Compared with other transformer-less dc-dc converters, the proposed converter is able to reduce the semiconductor voltage/current stress and therefore achieve the high efficiency. Simulation and experimental results verified the performance of the proposed TICC converter.

1 Introduction

Nowadays, the insulation level of PV panels has been developed to reach 1,500 V or even higher to improve the operational efficiency and reduce the construction cost of PV plants. It is claimed that the increment of PV maximum voltage from 1,000 to 1,500 V can lead to 15%–85% saving in conductor mass of cables and 25%–60% saving in the number of combiner boxes (Gkoutioudi et al., 2013). In addition, a high efficiency can be achieved by the reduced current on the dc bus and ac output and the larger operational range of inverters (Serban et al., 2015). However, the increased voltage level also brings some problems. In specific, the high-input PV voltage results in large mismatch power losses among PV panels caused by shadows, manufacturing tolerances, dirtiness, and so on (Kjaer et al., 2005). In addition, the high dc-link voltage leads to high voltage stress on semiconductor devices and a high common mode voltage, especially in the traditional two-level converters.

Currently, there are three widely used grid-tied PV inverters, which are the centralized inverter, the string or multi-string inverter, and the ac module or the module integrated converter (MIC) (Moghadasi et al., 2018). Among these converters, the centralized inverter and string or multi-string inverter are widely used in large-scale PV plants. Centralized inverters are usually connected to several PV arrays, each of which consists of many PV panels connected to the inverter dc-link, which is simple, reliable, and efficient (Karanayil et al., 2019). However, this configuration can only provide a single MPPT operation, and hence, it will increase the mismatch loss with the increment of PV panels in series. Thus, although the insulation voltage level of PV panels has reached 1,500 V, the voltage of PV strings may not be suitable to reach such a high voltage level. Therefore, there is usually a trade-off between the voltage level and mismatch losses. Some works have been carried out to solve this problem (Park et al., 2013; Choi et al., 2015; Choudhury et al., 2016; Karanayil et al., 2019; Yan et al., 2019). In specific, a general control scheme for the dual-input three-level inverter shown in Figure 1A was proposed to track the maximum power points (MPPs) of two PV arrays independently (Yan et al., 2019). Moreover, an auxiliary power converter was proposed to operate under serious partial shading to reduce mismatch losses among PV arrays as shown in Figure 1B (Karanayil et al., 2019).

FIGURE 1

FIGURE 1. (A) Dual-input three-level inverter. (B) Dual-input three-level inverter with an auxiliary power converter. (C) PV-to-PV DPP converter. (D) PV-to-bus DPP converter. (E) PV-to-virtual bus converter.

To improve the energy harnessing ability and reduce the switching voltage, several series differential power processing (DPP) architectures have been proposed (Shenoy et al., 2013; Stauth et al., 2013; Olalla et al., 2015), which are able to achieve the high efficiency by reducing the power rating of converters. As shown in Figures 1C–E, these series DPP architectures can be mainly classified into three groups: PV-to-PV DPP architectures, PV-to-bus architectures, and PV-to-virtual bus architectures. Regardless of the specific DPP architectures, each PV string can operate at its MPP. However, the total output voltage of the DPP converters is determined by the sum of the MPP voltages of all PV strings, which obviously makes DPP converters lack the voltage boost capability.

Another way to increase the voltage level of PV systems without too much PV panels connected in series is to use the two-stage PV systems with the front-end voltage boost capability. It can provide several advantages, such as a high energy yield and flexibility in plant design (Agamy et al., 2014). Although the distributed converters will lead to the decrease in conversion efficiency as well as an increase in cost per unit power as compared with the centralized converters, an annual energy yield gain of 6%–8% can be achieved to compensate the losses and cost of the additional converters (Elasser et al., 2010). In two-stage PV systems, the boost converter is widely used to step up the input PV voltage. Compared with the two-level inverter, the multi-level inverter can reduce the common mode voltage and improve the operational efficiency. Thus, the three-level boost converter can be assumed in front to reduce the voltage stress on semiconductor devices (Jung-Min Kwon et al., 2008; Tofoli et al., 2015). In Abdullah et al., 2014, a five-level diode-clamped inverter with the three-level boost converter was proposed to output a balanced five-level switching voltage, which further reduces the voltage stress.

Although the boost converter and three-level boost converter can step up the input voltage, they are more efficient when their input voltage is close to their output voltage as indicated in Zientarski et al., 2019. However, a higher input voltage means more PV panels in series and thus more mismatch losses. Therefore, it brings a trade-off between the converter efficiency and mismatch loss as the voltage level of the PV system increases. To overcome such a problem, a dual-input central capacitor (DICC) converter as shown in Figure 2A was proposed to simultaneously track two MPPs and then the input voltage of each PV array and semiconductor voltage/current stress of the converter can be reduced (Chen et al., 2017). Moreover, compared with DPP converters, DICC can maintain the dc-link voltage when the PV array voltage varies, which guarantees its energy harnessing ability. However, it is observed that both DPP converters and the DICC converter need an additional dc-link capacitor stage when they are connected to the multi-level rear-end inverters since these topologies have no distinct neutral point.

FIGURE 2

FIGURE 2. (A) Dual-input central capacitor converter. (B) Three-input central capacitor converter.

Being different, this paper proposes a three-input central capacitor (TICC) dc-dc converter, which can track the MPPs of three PV sources independently. It combines the merits of DPP converters and traditional boost converters, reducing the mismatch loss and voltage/current stress as DPP converters and keeping a constant dc-link voltage as boost converters. Besides, it has a distinct neutral point, ensuring that it can be connected to the popular three-level inverter directly. Moreover, by regulating the power transfer of three input PV sources, the proposed converter can help balance the three-level dc-link voltage. The configuration principle of the TICC converter can be extended to build the generalized topologies for involving more PV sources. This paper is organized as follows: Section 2 analyzes the operational principles and scalability of the proposed converter. Then, its control scheme is elaborated in Section 3. After that, a comparative study with its counterparts for high-voltage distributed PV architectures is presented in Section 4. Finally, Matlab simulations and an experiment prototype verified the performance of the proposed dc-dc converter.

2 Operational Principles and Scalability of the TICC Converter

2.1 Operational Principles of the Proposed Converter

The proposed three-input central capacitor converter is drawn in Figure 2B, where six capacitors are in series to power the inversion stage. As a result, the dc-link voltage is divided by the capacitors in series, which reduces the voltage stress on semiconductor devices and provides the necessary neutral point for connecting the rear-end multi-level inverters. Moreover, the output dc voltage V_bus is equal to the voltage sum of six capacitors V_CX (X = 1–6), which can be written as

$\{\begin{array}{c}{\mathit{V}}_{\mathit{bus}}={\mathit{V}}_{\mathit{up}}+{\mathit{V}}_{\mathit{down}}\\ {\mathit{V}}_{\mathit{up}}={\mathit{V}}_{\mathit{C}1}+{\mathit{V}}_{\mathit{C}2}+{\mathit{V}}_{\mathit{C}3}\\ {\mathit{V}}_{\mathit{down}}={\mathit{V}}_{\mathit{C}4}+{\mathit{V}}_{\mathit{C}5}+{\mathit{V}}_{\mathit{C}6}\end{array}(1)$

where V_up and V_down are the upper and lower half parts of the dc bus voltage, respectively. Then, PV sources PV1 and PV3 are parallel with capacitors C₁ and C₆, respectively, and PV source PV2 is parallel with capacitors C₃ and C₄, which makes the equivalent input voltage increase 3-fold.

The proposed converter consists of four cascaded buck-boost converters, as illustrated in Figure 3. To distinguish the four buck-boost converters, they are defined as an upper converter, an upper central converter, a lower central converter, and a lower converter from top to bottom. The upper converter and lower converter can regulate the output power of PV1 and PV3, respectively. Moreover, the upper central and lower central converters could regulate the output power of PV2 together.

FIGURE 3

FIGURE 3. Power flow diagram of the proposed converter.

As shown in Figure 3, each buck-boost converter transfers part of the output power of PV sources to the central capacitor C₂ and C₅. Moreover, the central capacitor discharges its energy by the dc-bus current I_bus. As long as the charging energy and discharging energy of the central capacitors C₂ and C₅ are balanced dynamically, the voltage of central capacitors can be well regulated. Therefore, the voltage of the central capacitor can vary as the output voltage of the PV source changes, and then the proposed converter can keep a constant dc-bus voltage, which distinguishes it from DPP converters. When the converter operates under CCM conditions, the relationship between the inductor currents and bus current can be calculated as

$\{\begin{array}{c}\left(1-{\mathit{d}}_1\right){\mathit{i}}_{\mathbf{L}1}+\left(1-{\mathit{d}}_2\right){\mathit{i}}_{\mathbf{L}2}={\mathit{I}}_{\mathbf{bus}}\\ \left(1-{\mathit{d}}_3\right){\mathit{i}}_{\mathbf{L}3}+\left(1-{\mathit{d}}_4\right){\mathit{i}}_{\mathbf{L}4}={\mathit{I}}_{\mathbf{bus}}\end{array}(2)$

where d_x (x = 1–4) is the duty cycle of switch S_x (x = 1–4). The voltage gain under CCM can be calculated as

$\{\begin{array}{c}{\mathit{V}}_{\mathbf{C}2}/{\mathit{V}}_{\mathbf{C}1}={\mathit{d}}_1/\left(1-{\mathit{d}}_1\right)\\ {\mathit{V}}_{\mathbf{C}2}/{\mathit{V}}_{\mathbf{C}3}={\mathit{d}}_2/\left(1-{\mathit{d}}_2\right)\\ {\mathit{V}}_{\mathbf{C}5}/{\mathit{V}}_{\mathbf{C}4}={\mathit{d}}_3/\left(1-{\mathit{d}}_3\right)\\ {\mathit{V}}_{\mathbf{C}5}/{\mathit{V}}_{\mathbf{C}6}={\mathit{d}}_4/\left(1-{\mathit{d}}_4\right)\end{array}(3)$

Therefore, the output dc voltage V_bus can be expressed as

${\mathit{V}}_{\mathbf{bus}}=\frac{1}{1-{\mathit{d}}_1}{\mathit{V}}_{\mathbf{PV}1}+{\mathit{V}}_{\mathbf{PV}2}+\frac{1}{1-{\mathit{d}}_4}{\mathit{V}}_{\mathbf{PV}3}(4)$

where V_PV1 and V_PV3 are the output voltages of PV sources PV1 and PV3, which are equal to V_C1 and V_C6, respectively, and V_PV2 is the output voltage of PV source PV2, which can be calculated as

${\mathit{V}}_{\mathbf{PV}2}={\mathit{V}}_{\mathbf{C}3}+{\mathit{V}}_{\mathbf{C}4}(5)$

The DCM of the proposed converter differs from CCM by having an extra interval during each switching cycle when the instantaneous inductor current reaches zero. The boundary condition between CCM and DCM is attained as follows:

${\mathit{I}}_{\mathit{L}}=\frac{{\mathit{V}}_{\mathbf{in}}\cdot \mathit{d}}{2\mathit{L}\cdot {\mathit{f}}_{\mathbf{sw}}}(6)$

where V_in is the input voltage on the capacitor of each buck-boost converter, and f_sw represents the switching frequency of the transistor. Like the buck-boost converter, DCM is likely to happen under low power and low inductance value conditions. The boost ratio under DCM can be expressed as

$\frac{{\mathit{V}}_{\mathit{cen}}}{{\mathit{V}}_{\mathit{PV}}}=\sqrt{1+\frac{3{\mathit{R}}_{\mathit{eq}}\cdot {\mathit{d}}^2}{8\mathit{L}\cdot {\mathit{f}}_{\mathbf{sw}}}}-1(7)$

where R_eq = V_bus/I_bus = V_bus²/(3V_PVI_PV), representing the equivalent load resistance of the inversion stage.

In addition, the DCM operation announces the merit of lower switching loss. Under DCM conditions, the transistors turn ON under zero current switching (ZCS), and also, the diodes turn OFF under ZCS. The reverse recovery current of the diode is well eliminated because the falling rate of diode current is limited by the inductor.

The three PV sources usually have the same specifications. However, in practice, their output power may be different and time-variant due to the variation of irradiance and some other factors, which can be expressed as

$0<{\mathit{P}}_{\mathbf{PVX}}\le {\mathit{P}}_{\mathit{max}}(8)$

where P_max is the maximum rated output power of PV sources. During operation, the output power of upper and lower half parts of the TICC converter should be balanced dynamically to make V_up equal V_down, respectively, which can be achieved by properly regulating four independent switches. In specific, there are 16 switching combinations in total as listed in Table 1. Because the upper converter and the lower converter can work independently, the switching combinations of the proposed converter are then divided into four states according to the working states of the upper central and lower central converters, which need to coordinate with each other to regulate the output power of PV2 and balance the dc-bus voltage.

TABLE 1

TABLE 1. Main operational states of the proposed converter.

State 1: Both S₂ and S₃ are turned ON. PV2 charges inductors L₂ and L₃, as shown in Figure 4A.

FIGURE 4

FIGURE 4. (A) State 1, (B) state 2, (C) state 3, and (D) state 4 of the proposed converter.

State 2: Only S₂ is turned ON. The energy from PV2 is stored in L₂, and inductor L₃ discharges its energy to the central capacitor C₅, as shown in Figure 4B.

State 3: Only S₃ is turned ON. The energy from PV2 is stored in L₃, and inductor L₂ discharges its energy to the central capacitor C₂, as shown in Figure 4C.

State 4: Both S₂ and S₃ are turned OFF. Inductors L₂ and L₃ discharge their energy to C₂ and C₅, respectively, as shown in Figure 4D.

It can be seen from State 2 and State 3 that the upper central converter and lower central converter can deliver differential power to capacitors C₂ and C₅, respectively. In specific, powers P_C3 and P_C4 absorbed by the upper central converter and lower central converter, respectively, from PV source PV2 can be expressed as

$\{\begin{array}{c}{\mathit{P}}_{\mathbf{C}3}={\mathit{V}}_{\mathbf{C}3}\cdot {\mathit{I}}_{\mathbf{PV}2}\\ {\mathit{P}}_{\mathbf{C}4}={\mathit{V}}_{\mathbf{C}4}\cdot {\mathit{I}}_{\mathbf{PV}2}\end{array}(9)$

Therefore, when the voltages on capacitors C₃ and C₄ are different, the upper central converter and lower central converter can send differential energy to capacitors C₂ and C₅, respectively, to balance the output voltage. In specific, the relationship between P_C3 and P_C4 should satisfy the following equation:

${\mathit{P}}_{\mathit{PV}1}+{\mathit{P}}_{\mathit{C}3}={\mathit{P}}_{\mathit{PV}3}+{\mathit{P}}_{\mathit{C}4}(10)$

Thus, the dc-link voltage can be balanced by regulating the power difference P_dif between P_C3 and P_C4, which can be derived as

${\mathit{P}}_{\mathbf{dif}}={\mathit{P}}_{\mathbf{C}3}-{\mathit{P}}_{\mathbf{C}4}={\mathit{V}}_{\mathbf{C}3}{\mathit{I}}_{\mathbf{PV}2}-{\mathit{V}}_{\mathbf{C}4}{\mathit{I}}_{\mathbf{PV}2}(11)$

where V_C3 and V_C4 can be expressed as

$\{\begin{array}{c}{\mathit{V}}_{\mathbf{C}3}=\left(1-{\mathit{d}}_2\right)\left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{PV}1}\right)\\ {\mathit{V}}_{\mathbf{C}4}=\left(1-{\mathit{d}}_3\right)\left({\mathit{V}}_{\mathbf{down}}-{\mathit{V}}_{\mathbf{PV}3}\right)\end{array}(12)$

Then, the power difference P_dif can be further calculated as

${\mathit{P}}_{\mathbf{dif}}=\left(1-{\mathit{d}}_3\right)\left[\left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{down}}\right)+\left({\mathit{V}}_{\mathbf{PV}3}-{\mathit{V}}_{\mathbf{PV}1}\right)\right]{\mathit{I}}_{\mathbf{PV}2}-\left({\mathit{d}}_2-{\mathit{d}}_3\right)\cdot \left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{PV}1}\right){\mathit{I}}_{\mathbf{PV}2}(13)$

Because V_PV1 is approximately equal to V_PV3 and V_up is approximately equal to V_down, the Eq. 13 can be simplified as

${\mathit{P}}_{dif}\approx -\left({\mathit{d}}_2-{\mathit{d}}_3\right)\cdot \left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{PV}1}\right){\mathit{I}}_{\mathbf{PV}2}(14)$

Thus, the upper central converter and lower central converter can help balance the power difference between P_PV1 and P_PV3 by regulating the difference between d₂ and d₃, and then the proposed converter can output a balanced three-level dc-bus voltage. The input power of PV2 can be derived as

$\begin{array}{c}{\mathit{P}}_{\mathbf{PV}2}={\mathit{P}}_{C3}+{\mathit{P}}_{C4}=\left(2-{\mathit{d}}_2-{\mathit{d}}_3\right)\cdot \left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{PV}1}\right)\cdot {\mathit{I}}_{\mathbf{PV}2}-\left(1-{\mathit{d}}_3\right)\\ \left[\left({\mathit{V}}_{\mathbf{down}}-{\mathit{V}}_{\mathbf{up}}\right)+\left({\mathit{V}}_{\mathbf{PV}1}-{\mathit{V}}_{\mathbf{PV}3}\right)\right]\cdot {\mathit{I}}_{\mathbf{PV}2}\left(1-{\mathit{d}}_3\right)\\ \left[\left({\mathit{V}}_{\mathbf{down}}-{\mathit{V}}_{\mathbf{up}}\right)+\left({\mathit{V}}_{\mathbf{PV}1}-{\mathit{V}}_{\mathbf{PV}3}\right)\right]\cdot {\mathit{I}}_{\mathbf{PV}2}\end{array}(15)$

Similarly, the Eq. 15 can be simplified as

${\mathit{P}}_{\mathbf{PV}2}\approx \left(2-{\mathit{d}}_2-{\mathit{d}}_3\right)\cdot \left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{PV}1}\right)\cdot {\mathit{I}}_{\mathbf{PV}2}(16)$

Then, the sum of d₂ and d₃ can also help regulate the output power of PV2. Thus, the proposed converter can regulate the power of three PV sources and balance the three-level dc-link voltage.

Under normal conditions, where the power difference among three PV sources is small, the upper converter and the lower converter can track the MPPs of PV1 and PV3, respectively. The upper central converter and the lower central converter can track the MPP of PV2 together and compensate the power difference between P_PV1 and P_PV3, as illustrated in Figure 5A.

FIGURE 5

FIGURE 5. Power flow diagrams of the TICC converter (A) when PV2 can compensate the power difference between PV1 and PV3 and (B) when PV2 cannot compensate the power difference between PV2 and PV3.

However, under some extreme conditions, where there is a large power mismatch among three PV sources as shown in Figure 5B, the unbalance of three-level dc-link voltage may occur. In specific, the proposed converter cannot keep a balanced output voltage when the power difference between P_PV1 and P_PV3 is larger than P_PV2, which can be expressed as

$\left|{\mathit{P}}_{\mathbf{PV}1}-{\mathit{P}}_{\mathbf{PV}3}\right|>{\mathit{P}}_{\mathbf{PV}2}(17)$

However, fortunately, the rear-end three-level inverter can help balance the output voltage of the proposed converter by regulating its PWM sequences (Lyu et al., 2015; Rivera et al., 2015; Tan et al., 2016). In such a case, PV2 sends all its power to compensate the power difference between P_PV1 and P_PV3, as shown in Figure 5B. The rest power difference is compensated by the rear-end three-level inverter, whose ability to balance the dc bus voltage varies with the different methods. For example, the method presented in Rivera et al., 2015, which used the SVM for the NPC inverter, can achieve the compensation ability as shown in the shaded area of Figure 6, which can be expressed as

${\mathit{\eta }}_{\mathit{n}}=\frac{12\mathit{\alpha }}{2\sqrt{3\mathit{\pi m}}}(18)$

FIGURE 6

FIGURE 6. Voltage balance limit of the NPC inverter using SVM.

Here, η_n is the limit of the maximum unbalanced power ratio between the unbalanced power and the output power, α is the maximum voltage drift that can be minimized by redistributing the dwell time allocation for redundant small vectors, and m is the modulation index of the NPC inverter. Thus, the NPC inverter can balance the dc bus voltage when the unbalanced power ratio is lower than the limit as expressed below:

$\frac{\left|{\mathit{P}}_{\mathit{PV}1}-{\mathit{P}}_{\mathit{PV}3}\right|-{\mathit{P}}_{\mathit{PV}2}}{{\mathit{P}}_{\mathit{PV}1}+{\mathit{P}}_{\mathit{PV}2}+{\mathit{P}}_{\mathit{PV}3}}<{\mathit{\eta }}_{\mathit{n}}(19)$

Therefore, even if any PV source suffers a permanent damage, the other two PV sources can still work well as long as the Eq. 19 is satisfied. When the three-level inverter is unable to balance the output voltage because the inverter needs more freedom to improve the grid-side current quality (Yaramasu and Wu, 2014) or the unbalanced power ratio is higher than the limit, a non-maximum power point tracking (non-MPPT) algorithm (also known as constant power generation) (Vekic et al., 2017; Liu et al., 2018; Tafti et al., 2018) is enabled to reduce the output power of PV1 or PV3 by forcing it to track the given power references.

2.2 Scalability of the Proposed Converter

To further extend the generalization of the proposed converter configuration, two methods are presented here to scale up the number of PV sources. The first method is to replace each PV source in the TICC converter with a DPP converter, as shown in Figure 7, whose advantage is that it can decouple the control of the TICC converter and each DPP converter, which is beneficial to the modular design. The second method is to embed four PV-to-PV DPP converters to the TICC converter as shown in Figure 8, which can also be seen as embedding two central capacitors in a PV-to-PV DPP converter. It is noted that there is a direct power exchanging path between the upper half part and the lower half part in Figure 8, which can help balance the dc-link voltage, and then the converter can output the qualified three-level voltages. The detailed operational principle of Figure 7 and Figure 8 will not be comprehensively elaborated because they are out of the scope of this paper.

FIGURE 7

FIGURE 7. Extended configuration of the TICC converter where each PV source is replaced with the DPP converter.

FIGURE 8

FIGURE 8. Extended configuration of the TICC converter where four PV-to-PV DPP converters are embedded.

3 Control Strategy of the Proposed Converter

3.2 Operational Principles of the Proposed Converter

In each sampling period, the output power of each PV source and the voltage balance limit η_n are calculated to allocate the balancing task between the proposed converter and the rear-end three-level inverter. The flow chart of their coordinated control scheme is demonstrated in Figure 9A.

FIGURE 9

FIGURE 9. Flow chart of (A) coordinated control scheme between the proposed converter and the rear-end inverter. (B) Switching the control mode of each PV source and generating its power reference at non-M.

When the inverter cannot balance the dc-link voltage or P_PV2 is enough to compensate the power difference between P_PV1 and P_PV3, which can be expressed as an Eq. 20

$\left|{\mathit{P}}_{\mathbf{PV}1}-{\mathit{P}}_{\mathbf{PV}3}\right|<{\mathit{P}}_{\mathbf{PV}2}(20)$

the voltage balance control (VBC) in the dc side is responsible to balance the dc-link voltage. Otherwise, the VBC in the ac side is enabled to help balance the dc-link voltage and all the output power of PV2 is sent to compensate the power difference between P_PV1 and P_PV3 in the dc side. Therefore, the power difference P_dif between P_C3 and P_C4, which determines the compensated power provided by PV2, can be calculated as

$\left|{\mathit{P}}_{\mathit{dif}}\right|={\mathit{P}}_{\mathit{PV}2}(21)$

Then, if the unbalanced power ratio is within the maximum voltage balance limit η_n as expressed in the Eq. 19, the VBC in the dc side or ac side can keep a balanced dc-link voltage when three PV sources work at their MPPs. Otherwise, PV1 or PV3 is forced to operate at the non-MPPT mode and track the given power reference until the possible maximum unbalanced power ratio is reduced to the voltage balance limit. The flow chart of switching the control mode of each PV source and generating its power reference at non-MPPT control is shown in Figure 9B. When the power difference of three PV sources is lower than the limit of the maximum unbalanced power ratio of the NPC inverter η_n as indicated in Eq. 19, the three PV sources can all work at the MPPT mode. Otherwise, the non-MPPT mode of PV1 or PV3 is enabled to balance the dc-link voltage. The power reference of the PV source at the non-MPPT mode can be calculated by

$\{\begin{array}{c}{\mathit{P}}_{\mathit{ref}1}=\frac{1+{\mathit{\eta }}_{\mathit{n}}}{1-{\mathit{\eta }}_{\mathit{n}}}\left({\mathit{P}}_{\mathit{PV}2}+{\mathit{P}}_{\mathit{PV}3}\right)\\ \mathit{or}\\ {\mathit{P}}_{\mathit{ref}3}=\frac{1+{\mathit{\eta }}_{\mathit{n}}}{1-{\mathit{\eta }}_{\mathit{n}}}\left({\mathit{P}}_{\mathit{PV}2}+{\mathit{P}}_{\mathit{PV}1}\right)\end{array}(22)$

Then, it can return to the MPPT mode until the possible maximum unbalanced power ratio is reduced to the voltage balance limit. The possible maximum unbalanced power ratio is given by

$\{\begin{array}{c}\frac{{\mathit{P}}_{\mathit{max}}-{\mathit{P}}_{\mathit{PV}2}-{\mathit{P}}_{\mathit{PV}3}}{{\mathit{P}}_{\mathit{max}}+{\mathit{P}}_{\mathit{PV}2}+{\mathit{P}}_{\mathit{PV}3}}<{\mathit{\eta }}_{\mathit{n}}\\ or\\ \frac{{\mathit{P}}_{\mathit{max}}-{\mathit{P}}_{\mathit{PV}1}-{\mathit{P}}_{\mathit{PV}2}}{{\mathit{P}}_{\mathit{max}}+{\mathit{P}}_{\mathit{PV}1}+{\mathit{P}}_{\mathit{PV}2}}<{\mathit{\eta }}_{\mathit{n}}\end{array}(23)$

where P_max is the maximum output power of PV sources.

Figure 10A shows the control scheme of the upper central and lower central converters. The P&Q method is used to track the MPP of PV source PV2 and provides the voltage reference V_{PV2_ref} (Qian Zhang et al., 2014). A double-loop control strategy is applied to control the converters (Tan and Middlebrook, 1995), in which the outer loop regulates the output voltage of PV2 by generating the current reference i_Lref and the inner loop regulates the average current of i_L2 and i_L3 and balances the dc-link voltage. A voltage balance component Δd is introduced to regulate the power difference between P_C3 and P_C4. When the VBC in the dc side is responsible to balance the dc-link voltage (Kim et al., 2018), Δd is given by the Eq. 24

$\mathit{\Delta d}=\mathit{k}{\mathit{p}}_{\mathbf{balance}}\left({\mathit{V}}_{\mathbf{up}}-{\mathit{V}}_{\mathbf{down}}\right)(24)$

where kp_balance is the proportional gain of the controller. As demonstrated in Section 2.1, the difference between d₂ and d₃ plays an important role in regulating P_dif. The relationship between duty ratios d₂ and d₃ can be calculated as

${\mathit{d}}_2-{\mathit{d}}_3=2{\mathit{G}}_{\mathbf{PI}}\left(\mathit{s}\right)\cdot \mathit{\Delta d}(25)$

Then, Δd can be used to regulate P_dif and is proportional to the difference between V_up and V_down, which therefore can be used to balance the three-level dc-link voltage. The sum of d₂ and d₃ can determine the value of P_PV2, which can be calculated as

${\mathit{d}}_2+{\mathit{d}}_3=2{\mathit{G}}_{\mathbf{PI}}\left(\mathit{s}\right)\cdot \mathit{D}(26)$

where D is the deviation between the current reference i_Lref and the average current of i_L2 and i_L3. Therefore, D can be used to control P_PV2.

FIGURE 10

FIGURE 10. (A) Control scheme of the upper central and lower central converters. (B) Control scheme of the upper and lower converters.

While the VBC in the ac side is enabled to balance the dc-link voltage, the power difference P_dif between P_C3 and P_C4 need to equal P_PV2. Because the sum of P_C3 and P_C4 equals P_PV2, P_C3 and P_C4 can be calculated as

$\{\begin{array}{c}{\mathit{P}}_{\mathit{C}3}=\{\begin{array}{c}\mathit{ }0,\mathit{ }{\mathit{P}}_{\mathit{PV}1}>{\mathit{P}}_{\mathit{PV}3}\\ {\mathit{P}}_{\mathit{PV}2},\mathit{ }{\mathit{P}}_{\mathit{PV}1}<{\mathit{P}}_{\mathit{PV}3}\end{array}\\ {\mathit{P}}_{\mathit{C}4}=\{\begin{array}{c}{\mathit{P}}_{\mathit{PV}2},\mathit{ }{\mathit{P}}_{\mathit{PV}1}>{\mathit{P}}_{\mathit{PV}3}\\ \mathit{ }0,\mathit{ }{\mathit{P}}_{\mathit{PV}1}<{\mathit{P}}_{\mathit{PV}3}\end{array}\end{array}(27)$

It can be seen from the Eq. 9 and Eq. 12 that P_C3 and P_C4 decrease to 0 when d₂ and d₃ increase to 1. Thus, to make P_dif equal P_PV2, P_C3 or P_C4 needs to decrease to 0 by controlling d₂ or d₃. Then, the voltage balance component Δd can be calculated as

$\mathit{\Delta d}=\{\begin{array}{c}\mathit{kp}\cdot (1-{\mathit{d}}_2),\mathit{ }{\mathit{P}}_{\mathit{PV}1}>{\mathit{P}}_{\mathit{PV}3}\\ \mathit{kp}\cdot ({\mathit{d}}_3-1),\mathit{ }{\mathit{P}}_{\mathit{PV}1}<{\mathit{P}}_{\mathit{PV}3}\mathit{ }\end{array}(28)$

where kp is the proportional gain of the controller.

The upper and lower converters also employ the double-loop control strategy, as shown in Figure 10B. The control scheme shown in Figure 9B is used to switch the control modes of PV1 and PV3 between the MPPT control and non-MPPT control. Then, the outer loop regulates the output power of PV sources by controlling their output voltage, and the inner loop controls the inductor current i_L by providing the duty cycle to the switch.

3.3 Non-Maximum Power Point Tracking Algorithm

There are several methods for PV sources to track the given power references (Vekic et al., 20172017; Liu et al., 2018; Tafti et al., 2018). Among them, the non-MPPT algorithm described in Liu et al., 2018 is used in this paper, whose flowchart is shown in Figure 11, where the comparison of dP/dU with zero is performed first to make a distinction between states in the unacceptable zone (left from the MPP) and desired zone (right from the MPP) (Vekic et al., 20172017). Then, a variable step ΔP is employed to reduce both the overshoot of the dc-link voltage and the active power oscillations, which reduces its value when P_k is close to P_ref. a is the coefficient of the power point tracking step.

FIGURE 11

FIGURE 11. Flowchart of the non-MPPT algorithm.

4 Performance Comparison and Passive Component Design

To evaluate the properties of the proposed converter, its performance has been compared with its counterparts including the traditional boost converter, interleaved boost converter, three-level boost converter, and dual-input central capacitor converter.

4.1 Analysis and Comparison of Device Quantity

The device quantity of the proposed converter and its counterparts has been compared from the aspects of total and average device quantity as listed in Table 2. The average device quantity is the ratio of total device quantity over the quantity of PV sources. It can be observed that although the total device quantity of the proposed converter increases, the average device quantity of the proposed converter is less than or almost equal to those of its counterparts.

TABLE 2

TABLE 2. Comparison of device quantity.

4.2 Analysis and Comparison of Semiconductor Device Stress

When the proposed converter operates under CCM and the output power and voltage of three PV sources are equal, the relationship between the input PV voltage V_PV and the output voltage V_bus can be derived from Eq. 29

$\{\begin{array}{c}{\mathit{V}}_{\mathbf{PV}}\cdot {\mathit{d}}_1=\frac{1}{2}\left({\mathit{V}}_{\mathbf{bus}}-3{\mathit{V}}_{\mathbf{PV}}\right)\cdot \left(1-{\mathit{d}}_1\right)\\ \frac{{\mathit{V}}_{\mathbf{PV}}}{2}\cdot {\mathit{d}}_2=\frac{1}{2}\left({\mathit{V}}_{\mathbf{bus}}-3{\mathit{V}}_{\mathbf{PV}}\right)\cdot \left(1-{\mathit{d}}_2\right)\end{array}(29)$

Also, when the output power and voltage of three PV sources are equal, the power transferred from PV1 and PV3 to the central capacitors is equal and PV2 transfers equal power to the central capacitor C₂ and C₅. Thus, the power transferred from PV1 to C₂ is twice the power transferred from PV2 to C₂. According to the method of power balance on the central capacitor C₂, the following equation can be derived:

$\{\begin{array}{c}\frac{2}{3}{\mathit{V}}_{\mathit{C}2}\cdot {\mathit{I}}_{\mathit{bus}}={\mathit{V}}_{\mathit{C}1}\cdot {\mathit{I}}_{\mathit{avg}\_\mathit{S}1}\\ \frac{1}{3}{\mathit{V}}_{\mathit{C}2}\cdot {\mathit{I}}_{\mathit{bus}}={\mathit{V}}_{\mathit{C}3}\cdot {\mathit{I}}_{\mathit{avg}\_\mathit{S}2}\end{array}(30)$

where V_C2 can be calculated as

${\mathit{V}}_{\mathit{C}2}=\frac{1}{2}\left({\mathit{V}}_{\mathit{bus}}-3{\mathit{V}}_{\mathit{PV}}\right)(31)$

and V_C1 and V_C3 can be calculated as

$\{\begin{array}{c}{\mathit{V}}_{\mathit{C}1}={\mathit{V}}_{\mathit{PV}}\\ {\mathit{V}}_{\mathit{C}3}={\mathit{V}}_{\mathit{PV}}/2\end{array}(32)$

Thus, the average currents through S₁ and S₂ can be calculated as

$\{\begin{array}{c}{\mathit{I}}_{\mathbf{avg}\_\mathbf{S}1}=\frac{\left({\mathit{V}}_{\mathbf{bus}}-3{\mathit{V}}_{\mathbf{PV}}\right)\cdot {\mathit{I}}_{\mathbf{bus}}}{3{\mathit{V}}_{\mathbf{PV}}}\\ {\mathit{I}}_{\mathbf{avg}\_\mathbf{S}2}=\frac{\left({\mathit{V}}_{\mathbf{bus}}-3{\mathit{V}}_{\mathbf{PV}}\right)\cdot {\mathit{I}}_{\mathbf{bus}}}{3{\mathit{V}}_{\mathbf{PV}}}\end{array}(33)$

Because the switches only conduct during turn-on intervals, their peak current stresses can be calculated as

$\{\begin{array}{c}{\mathit{I}}_{\mathbf{peak}\_\mathbf{S}1}=\frac{{\mathit{I}}_{\mathbf{avg}, \mathbf{IGBT}\_\mathbf{S}1}}{{\mathit{d}}_1}=\frac{\left({\mathit{V}}_{\mathbf{bus}}-{\mathit{V}}_{\mathbf{PV}}\right){\mathit{I}}_{\mathbf{bus}}}{3{\mathit{V}}_{\mathbf{PV}}}\\ {\mathit{I}}_{\mathbf{peak}\_\mathbf{S}2}=\frac{{\mathit{I}}_{\mathbf{avg}, \mathbf{IGBT}\_\mathbf{S}2}}{{\mathit{d}}_2}=\frac{\left({\mathit{V}}_{\mathbf{bus}}-2{\mathit{V}}_{\mathbf{PV}}\right){\mathit{I}}_{\mathbf{bus}}}{3{\mathit{V}}_{\mathbf{PV}}}\end{array}(34)$

Here, the inductor current ripple has been neglected for simplicity. Similarly, the average current of diodes D₁ and D₂ can be expressed as

$\{\begin{array}{c}{\mathit{I}}_{\mathbf{avg}\_D1}=2{\mathit{I}}_{\mathbf{bus}}/3\\ {\mathit{I}}_{\mathbf{avg}\_\mathbf{D}2}={\mathit{I}}_{\mathbf{bus}}/3\end{array}(35)$

The processed maximum power of each semiconductor device can be derived by multiplying its peak voltage stress by its peak current stress. The comparison of semiconductor device stress is listed in Table 3. It can be seen that the voltage and current stresses of transistors and diodes in the proposed converter are mostly lower than those of its counterparts. Although more devices have been used, the sum of the processed maximum power of all switches and diodes for the TICC converter is the smallest.

TABLE 3

TABLE 3. Comparison of semiconductor device stress.

Figure 12 illustrates the relationship between boost ratio, voltage stress, current stress, and duty ratio when the input voltage V_PV equals to 100 V and the current of dc bus I_bus equals to 1 A, where their equations are listed in Table 4.

FIGURE 12

FIGURE 12. (A) Boost ratio, (B) peak current stresses of transistors/diodes, (C) peak voltage stresses of transistors/diodes, (D) average current stresses of transistors/diodes vs. duty ratio.

TABLE 4

TABLE 4. Comparison of semiconductor device stress.

It can be seen that the boost ratio has nearly tripled and the peak and average current stresses have been halved, compared with the three-level boost converter. Although the peak voltage stress has nearly doubled when the duty ratio is the same, the voltage stress under the same output voltage is reduced as listed in Table 3.

4.3 Analysis and Comparison of Power Loss

As analyzed in Dusmez et al., 2015, the three-level boost converter shows its superior efficiency performance over the traditional boost converter and interleaved boost converter. Therefore, to analyze the efficiency performance of the proposed converter, the proposed TICC converter can be only compared with three-level boost (THB) converters shown in Figure 13 under the same input and output conditions. The loss calculation is based on the parameters listed in Table 5. The calculation process of the semiconductor losses is composed of two steps. First, the loss-calculation model for a single device (IGBT or diode), which satisfies the requirement of the maximum conduction current and withstand voltage, is established by using the method of curve fitting to get the function relationship between the collector current and turn-on losses, the function relationship between the collector current and turn-off losses, and so on. Here, a datasheet of the IGBT module from Infineon is used to establish the loss-calculation model (Infineon, 2017). Then, the switching and conduction losses during each switching period can be obtained from the loss-calculation model in Agamy et al., 2014.

FIGURE 13

FIGURE 13. Three three-level boost converters.

TABLE 5

TABLE 5. Parameters for loss calculation.

The semiconductor losses are composed of IGBT’s switching losses and conduction losses, the diode’s reverse-recovery losses, and conduction losses, which can be calculated as

$\{\begin{array}{c}{\mathit{P}}_{\mathbf{switch}\_\mathbf{IGBT}}=\left({\mathit{E}}_{\mathbf{on}}\left({\mathit{i}}_{\mathbf{peak}}\right)+{\mathit{E}}_{\mathbf{off}}\left({\mathit{i}}_{\mathbf{peak}}\right)\right)\cdot \frac{{\mathit{V}}_{\mathbf{sw}}}{{\mathit{V}}_{\mathbf{rated}}}\cdot {\mathit{f}}_{\mathbf{sw}}\\ {\mathit{P}}_{\mathbf{con}\_\mathbf{IGBT}}={\mathit{I}}_{\mathbf{avg}\_\mathbf{IGBT}}\cdot {\mathit{V}}_{\mathbf{CE}}\left({\mathit{i}}_{\mathbf{peak}}\right)\\ {\mathit{P}}_{\mathbf{rec}\_\mathbf{diode}}={\mathit{E}}_{\mathbf{rec}}\left({\mathit{i}}_{\mathbf{peak}}\right)\cdot \frac{{\mathit{V}}_{\mathbf{sw}}}{{\mathit{V}}_{\mathbf{rated}}}\cdot {\mathit{f}}_{\mathbf{sw}}\\ {\mathit{P}}_{c\mathbf{on}\_\mathbf{diode}}={\mathit{I}}_{\mathbf{avg}\_\mathbf{diode}}\cdot {\mathit{V}}_{\mathit{F}}\left({\mathit{i}}_{\mathbf{peak}}\right)\end{array}(36)$

where P_{switch_IGBT} and P_{con_IGBT} represent the switching and conduction power losses of IGBTs, and E_on (i_peak) and E_off (i_peak) refer to the turn-on and turn-off energy losses of IGBT, which are the functions of the collector current i_peak that passes through the IGBT. V_sw is the practical switching voltage of the switching process, V_rated is the rated switching voltage of the switching process, and f_sw is the switching frequency. I_{avg_IGBT} and I_{avg_diode} are the average currents that pass through IGBT and diode, respectively. V_CE (i_peak) is the collector-emitter voltage of IGBT, which is the function of the collector current i_peak. P_{rec_diode} and P_{con_diode} are the reverse-recovery and conduction power losses of diodes, respectively. E_rec (i_peak) is the reverse-recovery energy loss of the diode, which is the function of the forward current i_peak that passes through the diode. V_F(i_peak) is the forward voltage of the diode, which is the function of the forward current i_peak.

The inductors can be selected by the software from Magnetics (Kjaer, 2004); then the corresponding losses of the inductor can be expressed as

${\mathit{P}}_{\mathbf{L}\_\mathbf{loss}}={\mathit{P}}_{\mathbf{core}}+{\mathit{P}}_{\mathbf{copper}}(37)$

where P_core and P_copper are the core loss and copper loss of the inductor, respectively, which can be calculated as

$\{\begin{array}{c}{\mathit{P}}_{\mathbf{core}}=\mathit{f}\left({\mathit{I}}_{\mathbf{dc}},{\mathit{I}}_{\mathbf{ripple}},{\mathit{f}}_{\mathbf{sw}},\mathit{L}\right)\\ {\mathit{P}}_{\mathbf{copper}}={\mathit{I}}_{\mathbf{dc}}^2{\mathit{R}}_{\mathbf{dc}}\end{array}(38)$

where I_dc is the effective dc current flowing through the inductor, which approximately equals i_peak. I_ripple is the high-frequency ripple current, which is usually 30% of the dc current passing through the inductor. R_dc is the dc resistance of the inductor, and L is the inductance that must be maintained by the inductor, which can be calculated as

$\mathit{L}=\frac{{\mathit{V}}_{\mathbf{in}}\cdot \mathit{d}}{{\mathit{I}}_{\mathbf{ripple}}\cdot {\mathit{f}}_{\mathbf{sw}}}(39)$

where V_in is the input charging voltage of the inductor and d is the duty cycle of the charging state of the inductor.

Figure 14A shows the evaluated efficiency of these two converters under different load conditions (10%–100%) as the input voltage varies, indicating a higher efficiency of the proposed TICC converter over the three-level boost converter when their input PV voltages are equal. Here, the capacitor losses are neglected since the equivalent series resistance of the capacitor is usually quite small, for example, dozens of milliohms. With the increment of input PV voltage, the efficiency of the three-level boost converter can be improved. However, it will bring more mismatch power losses between PV modules. Figures 14B–E shows the fractions of power dissipated by the IGBT’s switching, the IGBT’s conduction, the diode’s reverse recovery, and the diode’s conduction operations, respectively. It can be seen that the proposed TICC converter reduces the IGBT switching and conduction losses and the diode’s reverse-recovery losses effectively, compared with three three-level boost converters. In addition, although one more inductor is used, the proposed converter has lower inductor losses as shown in Figure 14F because the currents flowing through the inductors of the TICC converter are low, which reduces its copper loss.

FIGURE 14

FIGURE 14. (A) Efficiency of the proposed TICC converter and three three-level boost converters, (B) fraction of power dissipated by IGBT’s switching among two converters, (C) fraction of power dissipated by IGBT’s conduction among two converters, (D) fraction of power dissipated by the diode’s reverse recovery among two converters, (E) fraction of power dissipated by the diode’s conducting among two converters, and (F) fraction of power dissipated on the inductor among two converters.

4.4 Passive Component Design

The inductor can be calculated by

$\mathit{L}=\frac{{\mathit{V}}_{\mathbf{in}}\cdot \mathit{d}}{{\mathit{I}}_{\mathbf{ripple}}\cdot {\mathit{f}}_{\mathbf{sw}}}(40)$

where V_in is the input charging voltage of the inductor and d is the duty cycle of the charging state of the inductor. I_ripple is the high-frequency ripple current, which is usually 30% of the dc current I_dc passing through the inductor. I_dc approximately equals i_peak, which is the peak current stress of transistors.

Then the voltage ripple factor K_C, which is important when we select the capacitor, can be calculated as

${\mathit{K}}_{\mathit{C}}=\frac{\mathit{\Delta }{\mathit{V}}_{\mathit{C}}}{{\mathit{V}}_{\mathit{C}}}(41)$

where V_C is the capacitor voltage and ΔV_C is the voltage ripple, which can be calculated as

$\mathit{\Delta }{\mathit{V}}_{\mathit{C}}=\frac{1}{\mathit{C}}{\displaystyle \int {\mathit{i}}_{\mathit{C}}\mathit{dt}}(42)$

There are three states of the central capacitor C₂ and C₅, as shown in Figure 15. In the first state (0 ∼ d₁T_s), the capacitor current I_C1 equals the dc bus current I_bus, which can be expressed as

${\mathit{I}}_{\mathit{C}1}=-{\mathit{I}}_{\mathit{bus}}(43)$

and in the second state (d₁T_s ∼ d₂T_s), the capacitor current I_C2 can be calculated as

${\mathit{I}}_{\mathit{C}2}={\mathit{I}}_{\mathit{L}1}-{\mathit{I}}_{\mathit{bus}}(44)$

where I_L1 is the current of inductor L₁. In the third state (d₂T_s ∼ T_s), the capacitor current I_C3 can be calculated as

${\mathit{I}}_{\mathit{C}3}={\mathit{I}}_{\mathit{L}1}+{\mathit{I}}_{\mathit{L}2}-{\mathit{I}}_{\mathit{bus}}(45)$

where I_L2 is the current of inductor L₂. The inductor currents I_L1 and I_L2 approximately equal I_peak, which can be calculated by Eq. 34. Then the voltage ripple on the central capacitor can be calculated as

$\mathit{\Delta }{\mathit{V}}_{\mathit{C}}=\frac{{\mathit{I}}_{\mathit{C}1}{\mathit{D}}_1{\mathit{T}}_{\mathit{S}}}{\mathit{C}}(46)$

where D₁ and D₂ are the conduction duty cycles of switches S₁ and S₂, respectively. Thus, the central capacitor can be calculated as

$\mathit{C}=\frac{{\mathit{I}}_{\mathit{bus}}{\mathit{D}}_1{\mathit{T}}_{\mathit{S}}}{{\mathit{V}}_{\mathit{C}}\cdot {\mathit{K}}_{\mathit{C}}}(47)$

and there are two states of the input capacitor, as shown in Figure 16. In the first state (0 ∼ dT_s), the capacitor current can be calculated as

${\mathit{I}}_{\mathit{C}4}={\mathit{I}}_{\mathit{PV}}-{\mathit{I}}_{\mathit{bus}}-{\mathit{I}}_{\mathit{L}}(48)$

In the second state (dT_s ∼ T_s), the capacitor current can be calculated as

${\mathit{I}}_{\mathit{C}5}={\mathit{I}}_{\mathit{PV}}-{\mathit{I}}_{\mathit{bus}}(49)$

Then the voltage ripple on the input capacitor can be calculated as

$\mathit{\Delta }{\mathit{V}}_{\mathit{C}}=\frac{{\mathit{I}}_{\mathit{C}5}(1-\mathit{D}){\mathit{T}}_{\mathit{S}}}{\mathit{C}}(50)$

Thus, the input capacitor can be calculated as

$\mathit{C}=\frac{\left({\mathit{I}}_{\mathit{PV}}-{\mathit{I}}_{\mathit{bus}}\right)\left(1-\mathit{D}\right){\mathit{T}}_{\mathit{S}}}{{\mathit{V}}_{\mathit{C}}\cdot {\mathit{K}}_{\mathit{C}}}(51)$

FIGURE 15

FIGURE 15. Central capacitor voltage and current in the TICC converter.

FIGURE 16

FIGURE 16. Currents of the inductor and input capacitor in the TICC converter.

5 Simulations and Experimental Results

The Matlab simulation model has been built to verify the performance of the proposed three-input central capacitor converter, whose corresponding circuit parameters are listed in Table 6. To simulate the irradiation variations on the grid-tied PV system, the irradiation level of PV2 varies from 950 W/m² to 650 W/m² at the time of 0.05 s and recovers to 950 W/m² at the time of 0.3 s, while the irradiation levels of PV1 and PV3 keep unchanged at 1,000 W/m² and 980 W/m². Figure 17A shows the simulation waveforms. When the irradiation level of PV source PV2 suffers a disturbance, its output power varies with the change of the irradiation level. It can be seen that half of the dc-link voltage is regulated steadily to 600 V and the grid currents are not deteriorated.

TABLE 6

TABLE 6. Parameters of the simulation model.

FIGURE 17

FIGURE 17. (A) Simulated waveforms when the PV2 irradiance declines from 950 W/m² to 650 W/m² at 0.05 s and recovers to 950 W/m² at 0.3 s, (B) simulated waveforms when the irradiation levels of PV2 and PV3 reduce from 950 W/m² to 450 W/m² and from 980 W/m² to 480 W/m², respectively, at 0.05 s and recover to 750 W/m² and 780 W/m², respectively, at 0.3 s, (C) simulated waveforms when the variation of the irradiation level of PV2 and PV3 is the same as that in the previous case, but the inverter is involved to balance the dc-link voltage, and (D) simulated waveforms when the irradiation level of PV1 reduces to 0 W/m² at 0.05 s and the irradiation level of PV2 reduces by 300 W/m² at 0.3 s.

Another scenario is defined to evaluate the performance of the proposed converter under non-MPPT control by disabling the dc-link voltage regulation capability of the rear-end inverter. The irradiation levels of PV2 and PV3 reduce from 950 W/m² to 450 W/m² and from 980 W/m² to 480 W/m², respectively, at the time of 0.05 s and recover to 750 W/m² and 780 W/m², respectively, at the time of 0.3 s, while the irradiation level of PV1 keeps unchanged at 1,000 W/m². At the time of 0.05 s, the output power of PV1 is higher than the sum of the output powers of PV2 and PV3, which enables the non-MPPT control of PV1. As a result, the output voltage of PV1 is controlled to rise up in order to reduce its output power. It can be seen that the output power of PV1 is then kept to a constant value, which equals the sum of the output powers of PV2 and PV3. Therefore, the three-level dc-bus voltage can still keep balanced as shown in Figure 17B. Moreover, at the time of 0.3 s, the sum of the output powers of PV2 and PV3 is larger than the maximum output power of PV1 and then PV1 recovers to MPPT control. The output power of PV1 recovers to the initial level. Thus, the proposed converter can balance the dc-link voltage independently.

The next case is to verify the performance of the coordinated control between the proposed converter and the rear-end three-level inverter when the unbalanced power ratio is lower than the power balance limit, where the variation of the irradiation level of three PV sources is the same as that in the previous case, but the inverter is able to balance the dc-link voltage. Although the output power of PV1 is higher than the sum of the output powers of PV2 and PV3 at the time of 0.05 s, the three PV sources can still work at their MPPs because the inverter can help balance the dc-link voltage, as shown in Figure 17C. Then at the time of 0.3 s, the output power of PV2 and PV3 increases with the variation of the irradiation level.

Finally, to show the performance of the proposed converter when any PV source suffers a permanent damage, the irradiation level of PV1 reduces to 0 W/m² at the time of 0.05 s and the irradiation level of PV2 reduces from 950 W/m² to 650 W/m² at the time of 0.3 s, while the irradiation level of PV3 keeps unchanged at 980 W/m². It can be seen from Figure 17D that PV2 and PV3 can still work at their MPPs before the time of 0.3 s, where the unbalanced power ratio is within the power balance limit. Here, the power balance limit is defined as 0.08. At the time of 0.3 s, a further decrease of the irradiation level of PV2 causes that the unbalanced power ratio exceeds the power balance limit. Therefore, the non-MPPT control of PV3 is enabled to track the given power reference and help balance the dc-link voltage. As shown in Figure 17D, the non-MPPT control and the VBC in the ac side can coordinate well to balance the dc-link voltage.

To further evaluate the performance of the proposed converter, an experimental prototype was built as shown in Figure 18, whose component values and circuit parameters are listed in Table 7. All control algorithms are programmed in a DSP TMS320F28335 from TI and an FPGA XC3S500E. Three independent PV strings are connected in front. Since the irradiance level cannot be flexibly controlled for the installed rooftop PV strings, this experimental prototype can only examine the steady-state operation and the transient operation where PV voltage references suffer sudden changes.

FIGURE 18

FIGURE 18. Experimental testbed.

TABLE 7

TABLE 7. Parameters of the experimental prototype.

Figure 19A shows the experimental results when the PV voltage reference suffers a sudden decline to examine the PV voltage tracking and dc-link voltage balancing capability of the proposed converter. The voltage reference of PV1 is reduced from 180 V to 150 V at instant t₁. It can be seen that the dc-link voltage can keep balanced automatically, and the grid voltage and grid currents are in phase. Figure 19B shows the experimental waveforms when the PV2 voltage reference rises up from 180 V to 190 V at instant t₂. After a transient process, half of the dc-link voltage can be regulated to the steady-state value of 315 V, guaranteeing the normal operation of the rear-end inverter.

FIGURE 19

FIGURE 19. Experimental waveforms when (A) PV1 reference declines from 180 V to 150 V at instant t₁ and (B) PV1 reference rises up from 180 V to 190 V at instant t₂.

To analyze the efficiency performance of the proposed converter, the proposed TICC converter is compared with three-level boost converters shown in Figure 20. Because it is difficult to evaluate the mismatch loss at different input voltages, they are compared under the same input and output conditions. The input PV strings are replaced with the dc sources to adjust the output power flexibly. Then, with the input voltage of 250 V and the output dc-link voltage of 1,000 V, the efficiencies of the proposed TICC converter and three-level boost converters under different input power conditions are measured using a power analyzer, which samples V_PV1, I_PV1, V_PV2, I_PV2, V_PV3, I_PV3, V_up, I_dc+,V_down, and I_dc−. Then the efficiency can be calculated by

$\mathit{\eta }=\frac{{\mathit{V}}_{\mathit{PV}1}{\mathit{I}}_{\mathit{PV}1}+{\mathit{V}}_{\mathit{PV}2}{\mathit{I}}_{\mathit{PV}2}+{\mathit{V}}_{\mathit{PV}3}{\mathit{I}}_{\mathit{PV}3}}{{\mathit{V}}_{\mathit{up}}{\mathit{I}}_{\mathit{dc}+}+{\mathit{V}}_{\mathit{down}}{\mathit{I}}_{\mathit{dc}-}}(52)$

where V_PVX and I_PVX (X = 1–3) are the output voltage and current of PV sources, respectively, V_up and V_down are the upper and lower half parts of the dc bus voltage, respectively, and I_dc+ and I_dc− are the dc bus currents. It can be seen from Figure 20 that the proposed converter can provide a higher efficiency under the same input and output voltage.

FIGURE 20

FIGURE 20. Measured efficiencies of the three-level boost converter and TICC converter under the same input voltage.

6 Conclusion

This paper proposes a three-input central capacitor converter for a high-voltage PV system, which can output a balanced three-level dc-link voltage and track the MPPs of three PV sources independently. The three-level structure enables it to be connected to the three-level inverter directly and reduces the voltage stress on semiconductors. Compared with the widely used boost and three-level boost converters, the proposed converter can reduce the mismatch losses and therefore has better energy harnessing ability due to the MPPT control of three split PV sources. Then, its operational principles and scalability are presented in detail. In addition, its corresponding control strategy is proposed to balance the three-level dc-link voltage when there is a large difference among the output power of three PV sources. A comparative study is carried out to demonstrate the advantages of the proposed converter, indicating its low semiconductor voltage/current stress and high efficiency. The performance of the three-input central capacitor converter along with its control strategy was verified by both simulation and experimental results.

Data Availability Statement

The original contributions presented in the study are included in the article/Supplementary Material; further inquiries can be directed to the corresponding author.

Author Contributions

XM and JL came up with the idea. XM is responible for carrying out the simulation and experiment verifications. GW and JF help check the simulation and experiment results.

Conflict of Interest

Author JL was employed by State Grid Weihai Power Supply Company. GW was employed by State Grid Yantai Power Supply Company.

The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s Note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations or those of the publisher, the editors, and the reviewers. Any product that may be evaluated in this article or claim that may be made by its manufacturer is not guaranteed or endorsed by the publisher.

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