Modeling of Gate Tunable Synaptic Device for Neuromorphic Applications

The emerging memories are great candidates to establish neuromorphic computing challenging non-Von Neumann architecture. Emerging non-volatile resistive random-access memory (RRAM) attracted abundant attention recently for its low power consumption and high storage density. Up to now, research regarding the tunability of the On/Off ratio and the switching window of RRAM devices remains scarce. In this work, the underlying mechanisms related to gate tunable RRAMs are investigated. The principle of such a device consists of controlling the filament evolution in the resistive layer using graphene and an electric field. A physics-based stochastic simulation was employed to reveal the mechanisms that link the filament size and the growth speed to the back-gate bias. The simulations demonstrate the influence of the negative gate voltage on the device current which in turn leads to better characteristics for neuromorphic computing applications. Moreover, a high accuracy (94.7%) neural network for handwritten character digit classification has been realized using the 1-transistor 1-memristor (1T1R) crossbar cell structure and our stochastic simulation method, which demonstrate the optimization of gate tunable synaptic device.

Introduction

Artificial intelligence has surpassed human beings in some areas, especially can help process complex and duplicate tasks constantly [1,2]. Traditional Von Neumann architecture is a mainstream architecture adopted to realize large scale AI computing, which separate the storage and calculation unit. The data transmission bus between memory circuit and CPU result in large power consumption, make the Von Neumann not suitable to execute the large scale AI processing in low-power environment such as the Internet of Things (IoT). Inspired by the structure of human brain, neuromorphic computing chips have been proposes and fabricated in a large scale [3,4]. To further improve the performance and energy efficiency, in recent years, emerging nonvolatile memory (NVM) based hardware for neuromorphic computing, which can emulate synapse function in a single device, has attracted much attention [5,6]. The continuous scaling down even down to sub-2 nm of NVM device also indicate that NVM is a great candidate to fabricate large scale high-density neuromorphic computing chips [7]. As for the underlying hardware components, numerous new devices that can integrate both storage and calculation functions have been investigated to establish brain-like circuits to accelerate the running time and reduce power dissipation. Among the NVMs device, RRAM is usually a simple two-terminal structure with a metal oxide layer between the two electrodes, which has been regarded as a promising next mainstream memory technology, due to its fast switching speed, excellent scalability, and non-volatile characteristic [8–11].

The resistance changes of a typical RRAM device are done by controlling the formation and the rupture of conductive filaments (CF). For most metal-oxide RRAM, the CFs are composed of oxygen vacancies [12]. Under the influence of an electric field, the metal-oxide is ionized into oxygen ions O²⁻ and oxygen vacancy. During the SET operation, O²⁻ are pulled out of the lattice and drift to the region near the top electrode/dielectric interface. The vacancies generated from the lack of oxygen are forming CFs which in turn are causing a dramatic increase in conductance. During the RESET operation, the reverse electric field repels the O²⁻ away from the top electrode/dielectric interface. The ions recombine with the vacancies, resulting in the CF rupture and therefore a decrease in conductance. Due to abrupt rupture and formation in resistive oxide layer, the RRAM device shows great advantages on switching speed, on/off ratio. On the other hand, the great scalability and recently proposed 3D integration technology of RRAM device.

In order to improve the characteristics of RRAM devices for neuromorphic computing applications, many studies have discussed different methods to enhance the control of the filament growth. One proposed solution is to use a gate tuning mechanism. This solution is effective to control the RRAM device set voltage and the On/Off ratio. This solution has another advantage as it is compatible with the traditional complementary-metal-oxide-semiconductor technology [13]. It is valuable to adopt a physics-based simulation combining the distribution of vacancies evolution with the device performances and analyze the physical mechanisms, so as to accurately predict its characteristics. In this work, a physics-based stochastic simulation method has been conducted in order to achieve this goal. The particle evolution and the IV characteristics under various gate bias are simulated and analyzed. The simulation results can guide researchers to optimize the gate bias that needs to be applied to obtain an optimal device characteristic. Moreover, oxide RRAM based neuromorphic-computing simulation using a handwritten recognition neural network has been trained on the MNIST dataset to verify the optimization of the applied bias, which obtained a 94.7% recognition accuracy and provide a guideline to tune the online learning accuracy based on novel NVM device.

Simulation Method

The Structure of Gate Tunable RRAM

Figure 1E demonstrates the whole framework to simulate gate tunable RRAM devices. Following the stochastic method mentioned in the flowchart, it is able to judge the particle drift behaviors and simulate the evolution of a device. A cycle contains two processes, the SET, and the RESET operation. The traditional RRAM structure possesses three layers, a material that has properties that can be altered sandwiched between two layers that serve as electrodes. A gate tunable oxide-based RRAM on the other side possesses graphene and an oxide layer in addition to the three aforementioned layers. Figure 1A show the structure of a basic device of this type. The graphene layer is inserted above the bottom electrode between the resistive layer and a SiO₂ layer. In our simulation, the graphene is modeled as a single metal atom layer. The gate bias is applied to the back gate, from which the electric field penetrates through the oxide and the graphene layer and influences the generation and the recombination probability inside the resistive layer. Figure 1B shows the growth of set process.

FIGURE 1

FIGURE 1. Device structure, tuning mechanism and simulation flowchart. (A) Schematic structure of a gate tunable RRAM under a positive, and a negative gate bias. (B) The Vo distributions during the set process and after set. (C) Flow chart of the simulation process adopted in this work to study the switching process and the device performance. (D) The tuning mechanism of gate electric field toward device performance and neuromorphic application.

The gate bias can help control the drift velocity of oxide ions and the generation barrier during the SET operation and the RESET operation. Based on the gate-tunable RRAM device, we establish a simulation method to simulate the behaviors of the device. Figure 1C shows the different steps that compose a simulation.

The Evolution Model of Oxide-based RRAM

During the SET operation, the generation of oxygen ions and vacancies are dominating. During the RESET operation, the recombination process is dominating. Both of the processes are related to the electric field present in the switching material. As the electric field and the vacancy distributions, the generation and recombination are updated every step. The generation and the recombination formulas are the followings

$\begin{array}{c}{\mathrm{P}}_g=f_0\exp \left(-\frac{\left(E_a-\gamma qE\right)}{k_{B}T}\right)\end{array}(1)$

$\begin{array}{c}{\mathrm{P}}_r=\mathrm{\beta }{\mathrm{C}}_{ion}{f}_0\exp \left(-\frac{E_a}{k_{B}T}\right)\end{array}(2)$

where $E_a$ is the migration barrier, $\gamma$ is the enhancement factor to the local electric field, ${\mathrm{C}}_{ion}$ is the concentration of oxygen ions, and the $E$ is the electric field which includes the gate electric field and the local electric field. During a DC sweep, ${\mathrm{P}}_g$ and ${\mathrm{P}}_r$ are calculated in all the mesh cells and at every step. They are then compared with a random number. If ${\mathrm{P}}_g$ is higher than the random number, a vacancy can be generated. Similarly, a vacancy can be recombined if ${\mathrm{P}}_r$ is higher than the random number generated. The vacancy distribution is updated this way for the next step. We can see from the ${\mathrm{P}}_{\mathrm{g}}$ formula that the electric field can control the migration barrier.

The Model of Gate Tunable Oxide-based RRAM

The resistance of the device can be divided into two main parts, the resistive layer, and the gate oxide layer. The graphene layer and top/bottom electrode are assumed to be perfect conductors. Due to the uniformity of the gate bias in the dielectric layer, the gate electric field is added to the original electric field in this layer. The formulas that describe the electric fields in the devices are

$\begin{array}{c}\mathrm{E}={\mathrm{E}}_{res-g}+{\mathrm{E}}_{res-d}\end{array}(3)$

$\begin{array}{c}{\mathrm{E}}_{res-g}=\frac{V_g-I{\rho }_{ins}\frac{l}{S}}{d_{res}}\end{array}(4)$

$\begin{array}{c}{\mathrm{E}}_{res-d}=-\nabla \mathrm{V}\end{array}(5)$

where ${\mathrm{E}}_{res-g}$ and ${\mathrm{E}}_{res-d}$ represents the electric field in resistive layer generated by the gate bias and the RRAM bias respectively, ${\rho }_{ins}$ is the resistivity of the insulator in the gate oxide layer, $d_{res}$ is the thickness of the resistive layer, $\mathrm{V}$ is the updated electric potential calculated using the Poisson equation, and $V_g$ is the gate bias.

The technique used in this study consist in regarding the whole resistive material as a network of resistors, and using a Kirchhoff model to compute the electric field and the potential in all the cell of the aforementioned network. Techniques using Kirchhoff’s Law fit well with conductive bridge random access memory experimental data [14]. In contrast to classical two terminals RRAM devices, our gate tunable oxide-based RRAM possesses three terminals. The leakage current from the back gate has to be considered. However, because of the high resistivity of the SiO₂, the leak current is far less than the outflow current from the bottom electrode, and can therefore be omitted [12].

Simulation Results and Discussion

After applying voltage bias at the gate electrode, the positive or negative gate electric field have different influences on the I-V characteristics. The generation rate is balanced with the recombination rate under the original condition without bias. When a positive electric field penetrates the resistive layer, the set voltage is increased. In this case, the generation probability is reduced while the recombination rate remains the same, and vice versa when the electric field is negative. Figure 2A presents the simulated DC sweep results without gate bias. The set voltage is around 1.255 V. Based on Eq. 1, it can be deduced that the reset time is inversely proportional to the drift velocity of the oxygen ions. Figure 2B shows the I-V results during the SET process with different gate biases after setting a compliance current of 10^–5 A. To present the variances of the device performance, a device-to-device simulation was conducted for 10 cycles and for every single gate bias. The results are shown in Figures 2C,D. Overall, both the set voltage and the On/Off ratio have an increasing trend as the applied gate bias is swept from negative to positive, which corresponds with the aforementioned results. Therefore, the increase of set voltage and On/Off ratio can be attributed to the filament evolution process. As Figure 1B shows, the increase of E-field in the resistive layer will result in the decrease of reset time. The exponential reduction trend mean that the reset time can be tuned by gate bias exponentially if we adopt the model in this work.

FIGURE 2

FIGURE 2. Characteristics of gate tunable oxide-based RRAM. (A) The IV curve of a single device without gate bias (B) The IV curve of the SET process of different devices with different gate biases. (C,D) display the distribution of the SET voltages and the On/Off ratios when the gate bias is set at −20 , −10, 0, and 10 V.

The read current and set current shown in Figures 3A,B have similar trend that negative or smaller positive gate bias cause the current shifting to larger magnitude of level and increase the distribution range. This’s can be explained that generation probability is threatened and the stochastic property is enhanced under strong E-field. On the other hand, to simulate the reset process, oxygen ions transport equation was numerically solved. As the E-field value increase, it can be seen that reset time would be decreased exponentially.

FIGURE 3

FIGURE 3. Simulated current distribution and reset process. (A) Read current distribution under different gate bias. (B) Set current distribution under different gate bias. (C) Oxygen ions distribution at different times. (D) The relationship of reset time (the time that oxygen ions move to another interface) and E-field.

Gate Tunable Oxide-Based RRAM for Neuromorphic Computing

A Ideal NVM device should be totally linear during potentiation and depression, and the conductance states would increase or decrease at a fixed step after applying positive pulse or negative pulse with identical magnitude. The other impact factors include On/Off ratio, cycle-to-cycle variations and device-to-device variations, all of which can deteriorate analog RRAM-based neuromorphic computing hardware towards application [15]. Moreover, the number of states can also determine the weight update precision. There are some efforts to improve the number of immediate states, and even 256 analogue states has been realized [16,17].

In this work, the gate tunable RRAM has been used to establish a neural network to investigate the gate tunable linearity and on/off ratio. In neuromorphic computing, the device characteristic highly determines the accuracy of the neural network. Figure 4 illustrated the whole circuit to implement two-layer perceptron (MLP) using RRAM crossbar arrays as core component. The adopted neural network consists of 400 neurons in input layer, 100 neurons in hidden layer and 10 neurons in output layer, as Figure 4A shows. The neurons are CMOS circuits to implement activation function. The training process use back propagation algorithm and stochastic gradient descent to update weight (Figure 4B). The adopted circuit system is based on a typical RRAM-based neural system [5].

FIGURE 4

FIGURE 4. The RRAM-based neuromorphic computing circuit. (A) The two layer MLP neural network including 400 neurons in input layer, 100 neurons in hidden layer and 10 neurons in output layer. (B) Neural structure consists of matrix-vector multiplication unit and activation function unit, while the sigmoid is used in back propagation and relu is used in feed forward. (C) RRAM-based 1T1R crossbar array for realizing synapse in neural network. With the same circuit, the first part illustrates the work mechanism of multiplication and summation, while the second part represents the weight update in BP.

In Figure 4C, the bit line (BL) is for applying input voltage or pulse voltage to calculate output in feed forward (FF) process or change the conductance state in back propagation (BP). The word line (WL) is used to set the gate voltage controlling on-off of transistor to determine the selected row which can implement weight update. According to the scheme, a simple and compact crossbar array structure is used as weight matrix to implement vector-matrix multiplication and weight update if pulse is applied.

Figure 5A shows the conductance versus pulse curve for different gate voltages. The highlighted data is the data that will be used for training the neural networks. For this experiment, we selected data that possess a linear coefficient larger than 0.9. The selected data has demonstrated that the additional gate in RRAM can further control the growth of the filament, which also improves the linearity and On/Off ratio of the linear segment of the conductance-pulse data. The device characteristics for neuromorphic computing gradually get better when the gate bias decrease from 5 to −10 V. Most notably, when −10 V is applied to the gate, the linearity of the devices can reach 0.9821. The Modified National Institute of Standards and Technology (MNIST) database has been used to train the network. The training result has been shown in Figure 5B, the array of devices possessing better linearity and On/Off ratio shows an improved recognition accuracy. With the 5 V back gate voltage, the devices have a lower On/Off ratio and lower linearity leading to poor results in accuracy. The optimized recognition accuracy can reach 94.8% under −10 V gate voltage. This result demonstrates that the optimized devices indeed improve the recognition accuracy when used in a neuromorphic application.

FIGURE 5

FIGURE 5. Gate tunable RRAM-based neural network. (A) Gradual switching behavior using 1 V amplitudes and 10 ns width constant pulses. (B) The online learning accuracy based on the RRAM device and our stochastic simulation method under different gate bias after 125 epochs.

Conclusion

This work proposed an effective method to simulate gate tunable RRAM devices. We employed a physics-based stochastic model to investigate the internal mechanism of the devices. The controllability of the parameters has a stable trend and is promising in practical applications. Furthermore, devices under appropriate bias have been used to compose a neural network for handwritten digit classification. This application of the simulated device into a real-world example has been done to authenticate the effectiveness of our framework for modeling circuit and neuromorphic systems. This work reveals the tunable mechanism of the gate tunable oxide-based RRAM and promotes the application of the device for neuromorphic computing.

Data Availability Statement

The raw data supporting the conclusion of this article will be made available by the authors, without undue reservation.

Author Contributions

HT proposed the idea. YS wrote the paper and tested the main code. YL wrote the paper and tested the code. All the authors revised the manuscript.

Funding

This work was supported by the National Key R&D Program (2020YFA0709800) and the National Natural Science Foundation (62022047, 61874065, 51861145202, U20A20168) of China. This work is also supported by the Young Elite Scientists Sponsorship Program by CAST under Grant 2018QNRC001, and by the Fok Ying-Tong Education Foundation under Grant 171051. This work was also supported by the Beijing National Research Center for Information Science and the Technology Youth Innovation Fund (BNR2021RC01007).

Conflict of Interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s Note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

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