Common Ground Nine-Level Boost Inverter for Grid-Connected PV Applications

The article discusses a nine-level switching capacitor-based common ground-type boost inverter for grid-connected photovoltaic applications. The proposed structure’s direct connection between the negative terminal of the input source and the grid neutral eliminates leakage current. The proposed topology uses eleven switches, two diodes, and three switching capacitors to produce a double voltage boost with nine different voltage levels. Self-balancing switching capacitors eliminate the need for sophisticated independent control algorithms. The maximum voltage stress on one of the three capacitors equals the input voltage, while it is equal to half of the input voltage on the other two switched capacitors. The various modes of operation and capacitance calculation are discussed in depth. A comprehensive comparison with various nine-level topologies has been conducted in terms of total component count, total standing voltage, capacitor voltage, and approximate cost to demonstrate the proposed topology’s benefits. A 400-W inverter prototype is constructed, and the experimental findings under various operating situations are reviewed.

Introduction

Transformerless inverters (TLIs) for photovoltaic (PV) technology are gaining more popularity due to their simple structure, absence of a transformer, smaller size, reduced weight, and higher efficiency (Islam et al., 2015). The absence of a transformer removes the galvanic isolation between the PV array and the grid, resulting in leakage current through the parasitic capacitance between the PV source and the ground (González et al., 2008; Li et al., 2015). The undesirable leakage current causes many issues related to personnel safety, degrading the PV array characteristics, increased current harmonic distortion, and electromagnetic interference (Sonti et al., 2017). Therefore, it is mandatory to address the leakage current issue in the non-galvanic inverters. Thus, many approaches have been made based on novel topology derivations, new control algorithms, and different pulse modulation schemes to minimize the leakage current (Khan et al., 2020). From the topological point of view, the TLIs mitigate the leakage current using any one of the following methods: 1) decoupling the source from the grid, 2) connecting the grid neutral to the midpoint of the DC link, and 3) direct connection of the source negative terminal with the grid neutral, i.e., both connecting points are at ground potential (Kumari et al., 2021c). The TLIs derived from conventional full bridge (FB) can mitigate the leakage current by decoupling the source and load on the DC side (DC decoupling) or on the AC side (AC decoupling) during the freewheeling mode. In DC decoupling, the high switching stress of the H5 topology (Victor et al., 2008) is shared by two power switches employed on the positive and negative buses, known as the H6 topology (Islam and Mekhilef, 2015). An AC decoupling topology with a highly efficient and reliable inverter concept (HERIC) is presented in Heribert et al. (2003). However, in DC and AC decoupling methods, the TLIs fail to minimize the leakage current completely. Other drawbacks of decoupling type TLIs include increased conduction losses caused by extra power switches and an inability to meet grid voltage without a boost converter at the input side. Another approach to confront current is to connect the mid-point of the DC link capacitor to the grid neutral, known as neutral point clamped (NPC) or active neutral point clamped (ANPC) topologies (Zhang et al., 2013; Debnath and Chatterjee, 2016; Kumari M. et al., 2021). The requirement of an additional front-end DC–DC boost power processing stage to meet the AC grid amplitude is the main disadvantage of NPC-type topologies. In both topologies (Siddique et al., 2020; Siwakoti et al., 2020), an active neutral point clamped (ANPC) inverter with boosting capability is presented. Since the output of these topologies is equal to the input, they still need front-end boost converters when dealing with the low-voltage paralleled PV string panels. An effective alternative to suppress the leakage current is common ground (CG)-type topologies, in which the common ground is shared between the source and the neutral side of the grid, eliminating the common mode voltage. A CG topology using switched capacitors as a virtual bus is presented in Gu et al. (2013). The switched capacitor is charged during the positive half cycle, and it acts as a virtual source during the negative half cycle to supply load. Like a conventional full-bridge inverter, the maximum output voltage of this topology is the same as the input DC-link voltage. Some five-level inverter topologies (Kadam and Shukla, 2017; Grigoletto, 2020; Sandeep et al., 2020) are presented based on the common ground type, but they are incapable of boosting the input voltage. By adding a switched or flying capacitor to the CG-type structure, the output voltage can be boosted while generating a multi-level output voltage waveform. The topologies of Vosoughi et al. (2020), Kumari et al. (2021b), and Mohamed Ali et al. (2022) overcome the shortcomings of the preceding topologies by boosting the output voltage to twice the input voltage with reduced power components. The topologies of Shaffer et al. (2018) and Sathik et al. (2021) have a CG-type structure with a voltage gain of 2 and 4, respectively. The main drawback of these topologies is the utilization of a higher number of power components to generate five-level output voltage. The topology Habib Khan et al. (2020) can operate in both buck and boost modes to provide the same AC output voltage, but it has a large inrush current. In recent times, a common ground structure with more output voltage levels and high voltage gain has attained more focus among researchers. Thus, a seven-level CG structure (Grigoletto, 2021) with triple voltage gain and nine-level CG type (Chen et al., 2022) with quadruple voltage gain is presented. To generate a seven-level output voltage, the topology (Grigoletto, 2021) requires a total component count of sixteen, which significantly increases the power loss. The high voltage stress of three times the input voltage on five switches and on one capacitor is the main issue with the topology (Chen et al., 2022). By keeping all the aforementioned issues in the literature, this article presents a new common ground type nine-level inverter (CG9-L) topology with the following features:

i) Single phase, nine-level output voltage with integrated boost operation (voltage gain is 2).

ii) The maximum voltage stress on capacitor is equal to the input voltage.

iii) The maximum voltage stress is equal to the output voltage.

iv) Inherent capacitor voltage balancing.

v) Leakage current is suppressed because of the common ground structure.

This article is presented as follows: the proposed topology and its operation followed by capacitance calculation, power loss calculation, result discussion, comparative analysis with other existing MLI’s, and conclusion.

Proposed CG9-L Inverter Topology

The proposed CG9-L circuit configuration is depicted in Figure 1A. Structurally, CG-9L is composed of eleven power switches (S₁ to S₉ and S_B), three switched capacitors (C₁, C₂, and C₃), and two diodes (D_a and D_b). The power switch S_B is bidirectional, and all the other switches are unidirectional. The maximum voltage across the switched capacitor C₁ is equal to the input voltage and that across the remaining two capacitors, C₂ and C₃, is equal to half of the input voltage. The proposed CG9-L design has an inherent voltage balancing feature, and thus, it does not require any additional control circuits or algorithms to maintain the voltage balance of the capacitors. The neutral of the load side and the negative terminal of the input DC source are connected to the ground to establish a common ground feature.

FIGURE 1

FIGURE 1. Topology and its modes of operation. (A)Proposed CG-9L topology, (B) V_o = 0.5V_in, (C) V_o = V_in, (D) V_o = 1.5V_in, (E) V_o = 2V_in, (F) V_o = 0, (G) V_o = −0.5V_in, (H) V_o = −V_in, (I) V_o = −1.5V_in, and (J) V_o = −2V_in.

Description of Output Levels

The nine output voltage levels, namely, 0.5 V_in, V_in, 1.5 V_in, 2 V_in, 0, −0. 5V_in, −V_in, −1.5 V_in, and −2 V_in, are synthesized, as shown in Figures 1B–J. Based on the different modes of operation, the switched capacitors C₁, C_2, and C₃ are charged and discharged during every switching cycle. The detailed description of all the operating states is given as follows:

First Positive Voltage Level

The first positive output voltage level of the proposed topology is generated by turning on switches S₁, S₄, S₆, S₉, and S_B to generate an output voltage level of 0.5V_in, as shown in Figure 1B. The load current completes its path through S_B, the anti-parallel diode of switches S₆ and S₄, D_a, and the negative terminal of the source. Here, the output voltage is positive, and the load current is negative. The capacitors C₁ and C₃ get charged during this mode of operation, and it is expressed as follows:

$\{\begin{array}{c}{V}_{C1}=V_{in},\\ V_{C2}=V_{C3}=V_{in}/2,\\ V_O=V_{in}-V_{C2}.\end{array}(1)$

Second Positive Voltage Level

The input source is directly connected to the load through the power switches S₁, S_7, and S₉, as shown in Figure 1C. The switches S₄ and S₆ are also turned on to charge the capacitors C₂ and C_3. Since all the three capacitors are connected in parallel with the input source during this mode of operation, they get charged. The capacitor voltage and output voltage are expressed as follows:

$\{\begin{array}{c}{V}_{C1}=V_{in},\\ V_{C2}=V_{C3}=V_{in}/2,\\ V_O=V_{in}.\end{array}(2)$

Third Positive Voltage Level

The power switches S₁, S₃, S₆, and S_B are switched ON, and output current is conducted. The input source and capacitor C₃ voltages are added together to deliver the load, as shown in Figure 1D. Here, the capacitor C₁ is charged, and C₃ is discharged. Here, the output voltage is written as follows:

$\{\begin{array}{c}{V}_{C1}=V_{in},\\ V_O=V_{in}+V_{C3}.\end{array}(3)$

Fourth Positive Voltage Level

The proposed topology’s maximum output voltage level is obtained by turning on the switches S₁, S₃, S₆, and S₇, as shown in Figure 1E. During this mode, the input source and capacitor voltages V_C2 and V_C3 cumulatively deliver the load requirement. The capacitor C₁ is connected in parallel with the input source and charged to V_in. The respective voltages are expressed as

$\{\begin{array}{c}{V}_{C1}=V_{in},\\ V_O=V_{in}+V_{C2}+V_{C3}.\end{array}(4)$

Zero Output Level

In this mode, the power switches S₄, S₆, and S₈ are switched ON to provide a freewheeling path for the load. As shown in Figure 1F, the switches S₁ and S₉ are turned ON to charge the capacitors C₁, C₂, and C₃. The respective voltages are expressed as

$\{\begin{array}{c}{V}_{C1}=V_{in},\\ V_{C2}=V_{C3}=V_{in}/2,\\ V_O=0.\end{array}(5)$

First Negative Voltage Level

The switches S₂, S₄, S₆, and S_B are triggered ON to generate an output voltage level of −0.5V_in, and the respective voltage level is shown in Figure 1G. Here, the output voltage is negative, and the load current is positive. The current flows through S_B, the anti-parallel diode of switches S₆, S₄, C₁, and S₂, and the negative terminal of the source. The output voltage is expressed as follows:

$V_O=-\left(V_{C1}+V_{C3}\right)=-V_{in}/2.(6)$

Second Negative Voltage Level

Here, the power switches S₂, S₄, S₆, and S₈ are triggered ON, and the respective current flow path is shown in Figure 1H. The capacitor C₁ is discharged to supply the load and it is written as follows:

$V_O=-\left(V_{C1}\right)=-V_{in}.(7)$

Third Negative Voltage Level

The power switches S₂, S₄, S₅, and S_B are switched ON, and the load current is conducted. The capacitors C₁ and C₂ are discharging to deliver the load. The respective current flow path is shown in Figure 1I, and the output voltage is expressed as follows:

$V_O=-\left(V_{C1}+V_{C2}\right)=-3V_{in}/2.(8)$

Fourth Negative Voltage Level

This mode of operation generates the negative maximum output voltage level, and the load current flow path is shown in Figure 1J. The power switches S₂, S₄, S₅, and S₈ are triggered ON. Here, all three capacitors are discharging to supply the load. The output voltage in this mode is written as

$V_O=-\left(V_{C1}+V_{C2}+V_{C3}\right)= -2V_{in}.(9)$

Capacitance Calculation

The three switched capacitors C₁, C₂, and C₃ in the proposed CG9-L topology are self-balanced using a series-parallel technique (Siddique et al., 2019). The selection of the capacitance value of these capacitors is important in switched capacitor topologies to achieve the desired output voltage waveform. Also, it involves ripple loss, size, and total cost of the inverter. The longest discharging time of capacitors has been used to calculate the capacitance value. The capacitances are estimated by considering the maximum allowable ripple limit of 10% of its maximum voltage (Liu et al., 2014). The time period to calculate the capacitance value is written using a typical nine-level output voltage waveform as follows:

$t_1=T_O/20 ; t_2=T_O/10;t_3=3T_O/20;t_4=T_O/5;t_5=T_O/4;t_6=3T_O/10;t_7=7T_O/20; t_8=2T_O/5; t_9=9T_O/20;$

where T_o is the period of the output voltage waveform. The charge on the capacitors C₁, C₂, and C₃ at the resistive load during its LDC period is estimated as follows:

$Q_{\text{SC},\text{ C}1-\text{R}}=2{\displaystyle \underset{t_1}{\overset{t_5}{\int }}{I}_{\text{OL}}\left(t\right)dt},(10)$

$Q_{\text{SC},\text{ C}2-\text{R}}=Q_{\text{SC},\text{ C}3-\text{R}}=2{\displaystyle \underset{t_3}{\overset{t_5}{\int }}{I}_{\text{OL}}\left(t\right)dt}.(11)$

The load current value for purely resistive load can be expressed as follows:

$\{\begin{array}{c}\frac{V_{in}}{2} , \frac{T_O}{20}\le t\le \frac{T_O}{10}\\ V_{in}, \frac{T_O}{10}\le t\le \frac{3T_O}{20}\\ \frac{3V_{in}}{2}, \frac{3T_O}{20}\le t\le \frac{T_O}{5}\\ 2V_{in}, \frac{T_O}{5}\le t\le \frac{T_O}{4}.\end{array}(12)$

From Equations 10 and 12, the charge on the capacitor C₁ during resistive load is estimated as

$Q_{\text{SC},\text{ C}1-\text{R}}=\frac{V_{in}\pi }{R_{LO}}.(13)$

The optimum value of the capacitance of capacitor C₁ when the load is purely resistive is calculated as

$C_{1\text{optm}-\text{R}}\ge \frac{\pi }{R_{LO}\times k\times \omega }.(14)$

From Equations 11 and 12, the charge on the capacitors C₂ and C₃ during the resistive load is calculated as

$Q_{\text{SC},\text{ C}2-\text{R}}=Q_{\text{SC},\text{ C}3-\text{R}}=\frac{7V_{in}\pi }{10R_{LO}}.(15)$

The optimum value of the capacitance of capacitors C₂ and C₃ when the load is purely resistive can be calculated as

$C_{2\text{optm}-\text{R}}, C_{3\text{optm}-\text{R}}\ge \frac{7\pi }{10R_{LO}\times k\times \omega }.(16)$

When the load is resistive-inductive (RL), the load current is expressed as follows:

$I_{\text{OL}}\left(\text{t}\right)=\sin \left(\omega t-\theta \right).(17)$

At resistive-inductive (RL) loading conditions, the charge on the capacitance of capacitors C₁, C₂, and C₃ is calculated as

$Q_{\text{SC},\text{ C}1-\text{RL}}=\frac{2I_{\text{mx}}}{\omega }\left[\cos \left(\frac{\pi }{10}-\theta \right)-\sin \theta \right],(18)$

$Q_{\text{SC},\text{ C}2-\text{RL}}=Q_{\text{SC},\text{ C}3-\text{RL}}=\frac{2I_{\text{mx}}}{\omega }\left[\cos \left(\frac{3\pi }{10}-\theta \right)-\sin \theta \right].(19)$

The optimum value of the capacitance of capacitors C₁, C₂, and C₃ during resistive-inductive (RL) loading can be written as follows:

$C_{1\text{optm}-\text{RL}}\ge \frac{2I_{\text{mx}}}{k\times \omega \times V_{in}}\left[\cos \left(\frac{\pi }{10}-\theta \right)-\sin \theta \right],(20)$

$C_{2\text{optm}-\text{RL}}=C_{3\text{optm}-\text{RL}}\ge \frac{2I_{\text{mx}}}{k\times \omega \times V_{in}}\left[\cos \left(\frac{3\pi }{10}-\theta \right)-\sin \theta \right].(21)$

where I_mx is the maximum load current.

Power Loss Calculation

The total power loss of a topology depends on three losses: switching losses, conducting losses, and ripple losses. The overall efficiency can be estimated as

$\eta =\frac{P_{OUT}}{P_{OUT}+P_{L-T}}=\frac{P_{OUT}}{P_{OUT}+P_{SL-T}+P_{CD-T}+P_{R-T}},(22)$

where $P_{SL-T},P_{CD-T}$, and $P_{R-T}$ are the total switching loss, total conduction loss, and total capacitor ripple loss.

Switching Losses

When a power switch transition happens, i.e., when turn ON to turn OFF or turn OFF to turn ON, voltage and current overlapping occurs (Babaei et al., 2014). This causes loss in the power switch called switching loss. The switching losses of each power switch during turning ON $\left(P_{S-on}\right)$ and OFF $\left(P_{S-off}\right)$ are calculated as follows (Mohamed Ali et al., 2019):

$P_{S-on}=N_{on}{\displaystyle \underset{0}{\overset{T_{on}}{\int }}v\left(t\right)\times i\left(t\right)}=\frac{V_{st-on}\times I_{st-on}\times T_{on}\times N_{on}}{6\text{T}},(23)$

where V_st-ON, I_st-ON, and T_ON are the voltage across the switch when it is turned ON, current through the power switch during ON period, and turn ON time of the power switch.

$P_{S-off}=N_{off}{\displaystyle \underset{0}{\overset{T_{off}}{\int }}v\left(t\right)\times i\left(t\right)}=\frac{V_{st-off}\times I_{st-off}\times T_{off}\times N_{off}}{6\text{T}},(24)$

where V_st-OFF, Is_t-OFF, and T_OFF are the open circuit voltage of the switch when it is turned OFF, current through the power switch before turning OFF the power switch, and turn OFF time of the power switch, respectively. The total switching loss can be expressed as

$P_{SL-T}=f\times \left(P_{S-on}+P_{S-off}\right).(25)$

Conduction Losses

The internal resistance of a power switch is the source of conduction losses when it is in conduction (Mohamed Ali et al., 2021). The total conduction loss is calculated using the equivalent circuit of the proposed CG9-L topology.

The conduction losses are estimated as

$\begin{array}{l}{P}_{cd,1}={\left(i_c+i_{L1}\right)}^2\left(R_{n-s}+R_{Esr}+R_{n-D}\right)+{\left(i_{L1}\right)}^2\left(R_{n-s}+R_{Esr}+R_{n-D}\right)+{\left(i_{L11}\right)}^2\left(2R_{n-s}+R_{Esr}\right)+\left(R_{n-s}+R_{Lo}\right),\\ P_{cd,2}={\left(i_c+i_{L2}\right)}^2\left(R_{n-s}+R_{Esr}+R_{n-D}\right)+{\left(i_{L2}\right)}^2\left(R_{n-s}+R_{n-D}\right)+{\left(i_{L21}\right)}^2\left(2R_{n-s}+2R_{Esr}\right)+ {\left(i_{L22}\right)}^2\left(R_{n-s}+R_{Lo}\right),\\ P_{cd,3}={\left(i_c+i_{L3}\right)}^2\left(R_{n-s}+R_{Esr}+R_{n-D}\right)+{\left(i_{L3}\right)}^2\left(4R_{n-s}+R_{Esr}+R_{Lo}\right),\\ P_{cd,4}={\left(i_c+i_{L4}\right)}^2\left(R_{n-s}+R_{Esr}+R_{n-D}\right)+{\left(i_{L4}\right)}^2\left(4R_{n-s}+2R_{Esr}+R_{Lo}\right),\\ P_{cd,-1}={\left(i_{L5}\right)}^2\left(4R_{n-s}+2R_{Esr}+R_{Lo}\right),\\ P_{cd,-2}={\left(i_{L6}\right)}^2\left(4R_{n-s}+R_{Esr}+R_{Lo}\right),\\ P_{cd,-3}={\left(i_{L7}\right)}^2\left(4R_{n-s}+2R_{Esr}+R_{Lo}\right),\\ P_{cd,-4}={\left(i_{L8}\right)}^2\left(4R_{n-s}+3R_{Esr}+R_{Lo}\right),\end{array}(26)$

where $R_{n-S},R_{n-D},and{R}_{Esr}$ are the on-state resistance of the switch, diode, and equivalent series resistance of capacitors. Also, i_c, i_L1-i_L8, i_L11, i_L12, i_L21, and i_L22 are charging current and load currents during different output voltage levels. The average conduction loss for one complete cycle is calculated as

$P_{cd,1}^1=2\times P_{cd,1}\left(\frac{t_2-t_1}{T_O}\right);P_{cd,2}^1=2\times P_{cd,2}\left(\frac{t_3-t_2}{T_O}\right);P_{cd,3}^1=2\times P_{cd,3}\left(\frac{t_4-t_3}{T_O}\right);P_{cd,4}^1=2\times P_{cd,4}\left(\frac{t_5-t_4}{T_O}\right);P_{cd,-1}^1=2\times P_{cd,-1}\left(\frac{t_{11}-t_{10}}{T_O}\right);P_{cd,-2}^1=2\times P_{cd,-2}\left(\frac{t_{12}-t_{11}}{T_O}\right);P_{cd,-3}^1=2\times P_{cd,-3}\left(\frac{t_{13}-t_{12}}{T_O}\right);P_{cd,-4}^1=2\times P_{cd,-4}\left(\frac{t_{14}-t_{13}}{T_O}\right).$

The total conduction loss is estimated as

$P_{CD-T}=P_{cd,1}^1+P_{cd,2}^1+P_{cd,3}^1+P_{cd,4}^1+P_{cd,-1}^1+P_{cd,-2}^1+P_{cd,-3}^1+P_{cd,-4}^1.(27)$

Capacitor Losses

The difference in voltage between the input DC source and the voltage across the capacitor causes capacitor ripple loss. The ripple voltage can be estimated as follows:

$\mathrm{\Delta }{V}_C=\frac{1}{C}{\displaystyle \underset{t_{\text{s}}}{\overset{t_{\text{e}}}{\int }}{i}_{\text{c}}\left(t\right) dt},(28)$

where t_s-t_e is the start and end time duration of the longest discharge of the capacitor.

The ripple loss can be calculated (Ponnusamy et al., 2020) as

$\mathrm{\Delta }{V}_{C1}=\frac{I_{\text{mx}}}{\pi \times f\times C_1}\left[\cos \left(\frac{\pi }{10}-\theta \right)-\sin \theta \right],(29)$

$\mathrm{\Delta }{V}_{C2}=\mathrm{\Delta }{V}_{C3}=\frac{I_{\text{mx}}}{\pi \times f\times C_{2/\left(3\right)}}\left[\cos \left(\frac{3\pi }{10}-\theta \right)-\sin \theta \right].(30)$

The total capacitor ripple loss can be calculated as follows:

$P_{R-T }=\mathrm{\Delta }{V}_{C1}+\mathrm{\Delta }{V}_{C2}+\mathrm{\Delta }{V}_{C3}.(31)$

The total loss of the proposed CG9-L can be calculated as follows:

$P_{L-T}=P_{SL-T}+P_{CD-T}+P_{R-T }.(32)$

Result Discussion

The 400-W experimental prototype of the proposed CG-9L inverter is built in the laboratory using G60N100 IGBT switches, HCPL-3120 drivers, 1000 μF capacitors, Texas Instrument TMS320F28379D digital controller launchpad, and RL load, and its performance is analyzed under various steady-state and dynamic conditions. The switching frequency of the proposed inverter topology is 2.5 kHz. An input voltage of 100 V and load combinations of 100 Ω, 50 + j100 Ω, and 100 + j100 Ω were chosen while analyzing the performance of the proposed topology. The steady-state performance of a proposed topology has been analyzed by using a resistive load of 100 Ω, and the obtained experimental results of the output voltage, output current, and voltage across the capacitors are shown in Figures 2A–C. It is observed that the output voltage is 200 V while applying a 100 V input, which verifies the boosting ability of the proposed topology. The steady-state operating condition at a series resistive-inductive load of R = 100 and L = 100 mH with a power factor of 0.95 is also tested, and the results are shown in Figure 2D. The rms value of load current is 1.26 A, and the voltage across capacitors C₁ and C₂ is 100 and 50 V, respectively. The dynamic operating conditions such as input change, load change period, and variations in modulation index values have been checked. The experimental results of an output voltage that varies from 160 to 200 V and an output current that varies from 1.5 to 1.85 A when the input voltage is changed from 80 to 100 V are shown in Figure 3A. The load is changed from Z₁ = 50 + j100Ω to Z₂ = 100 + j100Ω to test the dynamic behavior. The output voltage is maintained at 200 V constantly, and the load current changes from 3.3 to 1.85 A. The corresponding results are shown in Figure 3C. Figure 3D shows the output voltage, current, capacitor voltage V_C2, and capacitor current i_C2 as the load is changed from R = 100 Ω to Z₂ = 100 + j100 Ω. The waveform shows that the capacitor voltage remains stable when the load changes, verifying the capacitor’s self-voltage balancing ability. Furthermore, the change in modulation index values has also been analyzed, and the respective waveforms are shown in Figures 3E,F. The modulation index values are changed from 1 to 0.7 to 0.5. When the modulation index is 1, all nine voltage levels have been obtained. But when it is 0.7 and 0.5, the levels of output voltage are decreased to seven levels and five levels, respectively. During all these dynamic analyses, the capacitor voltages are maintained constantly with allowable ripple, confirming the self-balancing of capacitors. The inrush current that arises due to the direct parallel connection between the input source and the switched capacitor is reduced by the high impedance path due to the incorporation of an inductor of 33 uH during experimentation. In the MATLAB/Simulink, a power loss of ∼10.9 W is obtained, whereas in the experiment, it is 15.4 W. The experimental efficiency is 96.2 % at ∼400 W, which is close enough to the simulation efficiency (97.3 %). Table 1 shows the power loss and efficiency during different loading conditions. The maximum simulation efficiency of 98.4% is achieved at ∼200 W with unity power factor, as shown in the simulation and experimental efficiency comparison in Figure 4.

FIGURE 2

FIGURE 2. Steady-state operating condition. (A) Experimental results of output voltage, load current, voltage across capacitors C₁, and capacitor current i_c1 at R = 100 Ω. (B) Experimental results of the output voltage, load current, voltage across capacitors C₂, and capacitor current i_c2 at R = 100 Ω. (C) Experimental results of output voltage, load current, voltage across capacitors C₃, and capacitor current i_c3 at R = 100 Ω. (D) Experimental results of output voltage, load current, voltage across capacitors C₁, and C₂ at Z₂ = 100 + j100 Ω.

FIGURE 3

FIGURE 3. Dynamic operating condition. (A) Experimental results of output voltage and load current during step input change. (B) Experimental waveform of capacitor voltages V_C1, V_C2, and V_C3 during step input change. (C) Experimental results of output voltage, load current, voltage, and current of switch S₃ during the load change period Z₁= 50 + j100 Ω to Z₂= 100 + j100 Ω. (D) Experimental results of output voltage, load current, voltage, and current of capacitors C₂, during the load change period R = 100 Ω to at Z₂ = 100 + j100 Ω. (E) Experimental results of the output voltage and load current during modulation index variations 1.0 to 0.7. (F) Experimental results of the output voltage and load current during modulation index variations 0.7 to 0.5.

TABLE 1

TABLE 1. Power loss and efficiency of the proposed topology.

FIGURE 4

FIGURE 4. Efficiency curve.

Comparative Analysis With Other Existing MLI’S

The merits of the proposed CG9-L topology in comparison with other recent 9-L topologies are listed in Table 2. The comparison is carried out on the basis of the number of components, N_sh—no. of switches, N_dv—no. of drivers, N_d—no. of diodes, N_cp—no. of capacitors, T_cc—total component count, T_c-L—number of components counts per level, total standing voltage (TSV_p.u.), cost function, negative level generation, efficiency, and approximate total cost.

i) The total component utilization ratio of the proposed topology is 2.9, which is less than all remaining topologies except the topologies presented in Iqbal et al. (2021) and Chen et al. (2022). It shows that the CG9-L topology uses minimum power components to produce higher output voltage levels. Despite having a lower component utilization ratio, the voltage stress on some of the switches is high, which is equal to four times the input voltage in topologies (Iqbal et al., 2021; Chen et al., 2022). The total component utilization ratio is calculated as follows:

$T_{C-L}= \left(N_{sh}+N_{dv}+N_d+N_{cp}\right)/N_L.(33)$

ii) Even though the topologies presented in Taghvaie and Adabi (2018) and Mohamed Ali et al. (2021) have a lower total standing voltage per unit, it employs more power components than the proposed topology, which increases the total power losses and reduces its efficiency.

iii) Next, the ratio of the total capacitor voltage to the maximum output voltage $V_{c-T}/V_{0-mx}$ is compared. The proposed topology uses three switched capacitors with a total capacitor voltage of V_o-mx, which is less than the topologies presented in Nakagawa and Koizumi (2019), Dhara and Somasekhar (2021), Sathik et al. (2021), and Chen et al. (2022) and equals the topologies presented in Zeng et al. (2017) and Mohamed Ali et al. (2021). Despite the low capacitor voltage ratio of the topologies in (Hinago and Koizumi, 2012; Taghvaie and Adabi, 2018; Sandeep, 2019; Iqbal et al., 2021; Jakkula et al., 2022), the common ground feature is absent. Furthermore, the component counts are high for topologies (Hinago and Koizumi, 2012; Taghvaie and Adabi, 2018; Jakkula et al., 2022), resulting in higher power losses.

iv) Furthermore, the cost function (C_f) is formulated as follows.

$C_f=\left(N_{sh}+N_{dv}+N_d+N_{cp}\right)+\alpha \times TS{V}_{p.u.}(34)$

and compared with all other topologies. The cost function is calculated with weight factors α = 0.5, 1, and 1.5, and the respective values are listed in Table 2. The cost function of the proposed topology is slightly higher than the topologies presented in (Iqbal et al., 2021; Chen et al., 2022) and less than all other topologies.

v) The approximate cost of the topologies in USD has been calculated and is listed in Table 3. To ensure a fair comparison, all topologies were considered with the goal of producing an output voltage of 400 V, and component ratings were chosen as shown in Table 3. From Table 3, it is clear that the cost of the proposed topology is the least, except for the topology presented in Iqbal et al. (2021).

TABLE 2

TABLE 2. Comparison with other recent 9L topologies.

TABLE 3

TABLE 3. Cost comparison of the proposed topology with other recent topologies.

The main advantage of the proposed topology is the suppression of leakage current due to its direct connection between the negative terminal of the source side and the neutral of the load side. This common ground connection feature is absent in all other structures except (Chen et al., 2022) listed in Table 2.

Conclusion

This study presented a nine-level inverter with leakage current suppression, voltage boosting, self-voltage balancing, and low voltage stress on capacitors based on a single-phase switching capacitor. The CG feature suppresses the leakage current, making the proposed topology suitable for the transformerless application. The functioning of the proposed topology and capacitance calculation has been discussed. A comprehensive comparison based on power components and capacitor voltage highlights the advantages of the recommended design over the other nine-level topologies. In addition, a complete cost examination confirmed the planned topology’s cost efficiency. The modelling and experimental findings showed that the suggested topology may be implemented under various dynamic operating circumstances without affecting the switched capacitors. Simulation yields a maximum efficiency of ∼97.3 % at 400 W, with a measured result of 96.2%. The suggested topology qualifies as a possible contender for grid-connected photovoltaic application due to the advantages discussed throughout this research.

Data Availability Statement

The original contributions presented in the study are included in the article/Supplementary Material; further inquiries can be directed to the corresponding author.

Author Contributions

NG: conceived the idea, designed the experiments, and wrote the manuscript. KV: supervision, formal analysis, review and editing, and validation. Both authors read and approved the final manuscript.

Conflict of Interest

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Publisher’s Note

All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors, and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.

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